FW Profile - C1 Implementation
FwSmTestCases.c
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1 
19 #include <stdio.h>
20 #include <stdlib.h>
21 #include "FwSmConfig.h"
22 #include "FwSmSCreate.h"
23 #include "FwSmDCreate.h"
24 #include "FwSmAux.h"
25 #include "FwSmPrivate.h"
26 #include "FwSmTestCases.h"
27 #include "FwSmMakeTest.h"
28 
32 extern int fwSm_logMarker[LOG_ARRAY_SIZE];
36 extern int fwSm_logState[LOG_ARRAY_SIZE];
40 extern int fwSm_logIndex;
41 
61 static int IsClone(FwSmDesc_t smDesc1, FwSmDesc_t smDesc2);
62 
63 static int IsClone(FwSmDesc_t smDesc1, FwSmDesc_t smDesc2) {
65 
66  /* Check that the two SMs share the same base descriptor */
67  if (smDesc1->smBase != smDesc2->smBase)
68  return 0;
69 
70  /* check that the two SMs have the same actions */
71  if (smDesc1->nOfActions != smDesc2->nOfActions) {
72  return 0;
73  }
74  for (i=0; i<smDesc1->nOfActions; i++)
75  if (smDesc1->smActions[i] != smDesc2->smActions[i]) {
76  return 0;
77  }
78 
79  /* check that the two SMs have the same guards */
80  if (smDesc1->nOfGuards != smDesc2->nOfGuards) {
81  return 0;
82  }
83  for (i=0; i<smDesc1->nOfGuards; i++)
84  if (smDesc1->smGuards[i] != smDesc2->smGuards[i]) {
85  return 0;
86  }
87 
88  /* Check that the ESMs of the second SM are structural
89  * clones of the ESMs of the first SM */
90  for (i=0; i<smDesc1->smBase->nOfPStates; i++)
91  if (smDesc1->esmDesc[i] != NULL)
92  if (!IsClone(smDesc1->esmDesc[i], smDesc2->esmDesc[i]))
93  return 0;
94  for (i=0; i<smDesc2->smBase->nOfPStates; i++)
95  if (smDesc2->esmDesc[i] != NULL)
96  if (!IsClone(smDesc2->esmDesc[i], smDesc1->esmDesc[i]))
97  return 0;
98  return 1;
99 }
100 
101 
102 /*------------------------------------------------------------------------------------------------- */
104  struct TestSmData sSmData;
105  struct TestSmData* smData = &sSmData;
106  FwSmDesc_t smDesc;
107 
108  /* reset log */
109  fwSm_logIndex = 0;
110 
111  /* Initialize data structure holding the state machine data */
112  smData->counter_1 = 0;
113  smData->counter_2 = 0;
114  smData->flag_1 = 0;
115  smData->flag_2 = 0;
116  smData->logBase = 0;
117 
118  /* Create first test SM */
119  smDesc = FwSmMakeTestSM1(smData);
120  if (smDesc==NULL)
121  return smTestCaseFailure;
122 
123  /* Check configuration of state machine */
124  if (FwSmCheck(smDesc) != smSuccess) {
125  FwSmRelease(smDesc);
126  return smTestCaseFailure;
127  }
128 
129  /* Check that state machine is not started */
130  if (FwSmIsStarted(smDesc) != 0) {
131  FwSmRelease(smDesc);
132  return smTestCaseFailure;
133  }
134 
135  /* Check that no ESM is returned because the SM is stopped */
136  if (FwSmGetEmbSmCur(smDesc) != NULL) {
137  FwSmRelease(smDesc);
138  return smTestCaseFailure;
139  }
140 
141  /* Start SM and check outcome of start operation */
142  FwSmStart(smDesc);
143  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)){
144  FwSmRelease(smDesc);
145  return smTestCaseFailure;
146  }
147 
148  /* Try re-starting the SM and check that nothing happens */
149  FwSmStart(smDesc);
150  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)){
151  FwSmRelease(smDesc);
152  return smTestCaseFailure;
153  }
154 
155  /* Check that state machine is started */
156  if (FwSmIsStarted(smDesc) != 1) {
157  FwSmRelease(smDesc);
158  return smTestCaseFailure;
159  }
160 
161  FwSmRelease(smDesc);
162  return smTestCaseSuccess;
163 }
164 
165 /*------------------------------------------------------------------------------------------------- */
167  struct TestSmData sSmData;
168  struct TestSmData* smData = &sSmData;
169  FwSmDesc_t smDesc2;
170 
171  /* reset log */
172  fwSm_logIndex = 0;
173 
174  /* Initialize data structure holding the state machine data */
175  smData->counter_1 = 0;
176  smData->counter_2 = 0;
177  smData->flag_1 = 0;
178  smData->flag_2 = 1; /* this forces the selection of the transition from IPS to FPS */
179  smData->logBase = 0;
180 
181  /* Create test SM */
182  smDesc2 = FwSmMakeTestSM2(smData);
183  if (smDesc2==NULL)
184  return smTestCaseFailure;
185 
186  /* Check configuration of state machine */
187  if (FwSmCheck(smDesc2) != smSuccess) {
188  FwSmRelease(smDesc2);
189  return smTestCaseFailure;
190  }
191 
192  /* Start SM and check outcome of start operation */
193  FwSmStart(smDesc2);
194  if ((smData->counter_1!=0) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc2)!=0)) {
195  FwSmRelease(smDesc2);
196  return smTestCaseFailure;
197  }
198 
199  /* Modify flags to force transition into S1 upon start */
200  smData->flag_1 = 1;
201  smData->flag_2 = 0;
202 
203  /* Start SM and check outcome of start operation */
204  FwSmStart(smDesc2);
205  if ((smData->counter_1!=1) || (smData->counter_2!=4) || (FwSmGetCurState(smDesc2)!=STATE_S1)) {
206  FwSmRelease(smDesc2);
207  return smTestCaseFailure;
208  }
209 
210  /* Verify the function to get the state of an embedded state machine in the case
211  * where a state has no embedded state machine */
212  if (FwSmGetCurStateEmb(smDesc2)!=-1) {
213  FwSmRelease(smDesc2);
214  return smTestCaseFailure;
215  }
216 
217  FwSmRelease(smDesc2);
218  return smTestCaseSuccess;
219 }
220 
221 /*------------------------------------------------------------------------------------------------- */
223  struct TestSmData sSmData;
224  struct TestSmData* smData = &sSmData;
225  struct TestSmData sEsmData;
226  struct TestSmData* esmData = &sEsmData;
227  FwSmDesc_t smDesc3;
228 
229  /* reset log */
230  fwSm_logIndex = 0;
231 
232  /* Initialize data structure to hold the data of the embedding state machine */
233  smData->counter_1 = 0;
234  smData->counter_2 = 0;
235  smData->flag_1 = 0;
236  smData->flag_2 = 0;
237  smData->logBase = 0;
238 
239  /* Initialize data structure to hold the data of the embedded state machine */
240  esmData->counter_1 = 0;
241  esmData->counter_2 = 0;
242  esmData->flag_1 = 0;
243  esmData->flag_2 = 1; /* this forces the selection of the transition from IPS to FPS */
244  esmData->logBase = 0;
245 
246  /* Create test SM */
247  smDesc3 = FwSmMakeTestSM3(smData, esmData);
248  if (smDesc3==NULL)
249  return smTestCaseFailure;
250 
251  /* Check configuration of state machine */
252  if (FwSmCheckRec(smDesc3) != smSuccess) {
253  FwSmReleaseRec(smDesc3);
254  return smTestCaseFailure;
255  }
256 
257  /* Check the function to retrieve the current sub-state */
258  if (FwSmGetCurStateEmb(smDesc3) != -1) {
259  FwSmReleaseRec(smDesc3);
260  return smTestCaseFailure;
261  }
262 
263  /* Start SM and check outcome of start operation */
264  FwSmStart(smDesc3);
265  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
266  FwSmReleaseRec(smDesc3);
267  return smTestCaseFailure;
268  }
269 
270  if ((esmData->counter_1!=0) || (esmData->counter_2!=2) || (FwSmGetCurStateEmb(smDesc3)!=0)) {
271  FwSmReleaseRec(smDesc3);
272  return smTestCaseFailure;
273  }
274 
275  FwSmReleaseRec(smDesc3);
276  return smTestCaseSuccess;
277 }
278 
279 /*------------------------------------------------------------------------------------------------- */
281  struct TestSmData sSmData;
282  struct TestSmData* smData = &sSmData;
283  FwSmDesc_t smDesc;
284 
285  /* reset log */
286  fwSm_logIndex = 0;
287 
288  /* Initialize data structure holding the state machine data */
289  smData->counter_1 = 0;
290  smData->counter_2 = 0;
291  smData->flag_1 = 0;
292  smData->flag_2 = 0;
293  smData->logBase = 0;
294 
295  /* Create test SM */
296  smDesc = FwSmMakeTestSM1(smData);
297  if (smDesc==NULL)
298  return smTestCaseFailure;
299 
300  /* Check configuration of state machine */
301  if (FwSmCheck(smDesc) != smSuccess) {
302  FwSmRelease(smDesc);
303  return smTestCaseFailure;
304  }
305 
306  /* Check that stopping a SM which is already stopped has no effect */
307  FwSmStop(smDesc);
308  if ((smData->counter_1!=0) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=0)) {
309  FwSmRelease(smDesc);
310  return smTestCaseFailure;
311  }
312 
313  /* Start SM (this brings it to state S1) */
314  FwSmStart(smDesc);
315  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
316  FwSmRelease(smDesc);
317  return smTestCaseFailure;
318  }
319 
320  /* Stop SM and check success */
321  FwSmStop(smDesc);
322  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
323  FwSmRelease(smDesc);
324  return smTestCaseFailure;
325  }
326 
327  FwSmRelease(smDesc);
328  return smTestCaseSuccess;
329 }
330 
331 /*------------------------------------------------------------------------------------------------- */
333  struct TestSmData sSmData;
334  struct TestSmData* smData = &sSmData;
335  struct TestSmData sEsmData;
336  struct TestSmData* esmData = &sEsmData;
337  FwSmDesc_t smDesc3;
338  FwSmDesc_t smDesc2;
339 
340  /* reset log */
341  fwSm_logIndex = 0;
342 
343  /* Initialize data structure to hold the data of the embedding state machine */
344  smData->counter_1 = 0;
345  smData->counter_2 = 0;
346  smData->flag_1 = 0;
347  smData->flag_2 = 0;
348  smData->logBase = 0;
349 
350  /* Initialize data structure to hold the data of the embedded state machine */
351  esmData->counter_1 = 0;
352  esmData->counter_2 = 0;
353  esmData->flag_1 = 1; /* this forces the selection of the transition from IPS to S1 */
354  esmData->flag_2 = 0;
355  esmData->logBase = 0;
356 
357  /* Create test SM */
358  smDesc3 = FwSmMakeTestSM3(smData, esmData);
359  if (smDesc3==NULL)
360  return smTestCaseFailure;
361 
362  /* Check configuration of state machine */
363  if (FwSmCheckRec(smDesc3) != smSuccess) {
364  FwSmReleaseRec(smDesc3);
365  return smTestCaseFailure;
366  }
367 
368  /* Start SM and check outcome of start operation */
369  FwSmStart(smDesc3);
370  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
371  FwSmReleaseRec(smDesc3);
372  return smTestCaseFailure;
373  }
374 
375  if ((esmData->counter_1!=1) || (esmData->counter_2!=2) || (FwSmGetCurStateEmb(smDesc3)!=STATE_S1)) {
376  FwSmReleaseRec(smDesc3);
377  return smTestCaseFailure;
378  }
379 
380  /* Stop SM and check outcome of stop operation */
381  smDesc2 = FwSmGetEmbSmCur(smDesc3); /* get the SM embedded in the current state of smDesc3 */
382  FwSmStop(smDesc3);
383  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=0)) {
384  FwSmReleaseRec(smDesc3);
385  return smTestCaseFailure;
386  }
387 
388  if ((esmData->counter_1!=5) || (esmData->counter_2!=2) || (FwSmGetCurState(smDesc2)!=0)) {
389  FwSmReleaseRec(smDesc3);
390  return smTestCaseFailure;
391  }
392 
393  FwSmReleaseRec(smDesc3);
394  return smTestCaseSuccess;
395 }
396 
397 /*------------------------------------------------------------------------------------------------- */
399  struct TestSmData sSmData;
400  struct TestSmData* smData = &sSmData;
401  struct TestSmData sEsmData;
402  struct TestSmData* esmData = &sEsmData;
403  FwSmDesc_t smDesc3;
404  FwSmDesc_t smDesc2;
405 
406  /* reset log */
407  fwSm_logIndex = 0;
408 
409  /* Initialize data structure to hold the data of the embedding state machine */
410  smData->counter_1 = 0;
411  smData->counter_2 = 0;
412  smData->flag_1 = 0;
413  smData->flag_2 = 0;
414  smData->logBase = 0;
415 
416  /* Initialize data structure to hold the data of the embedded state machine */
417  esmData->counter_1 = 0;
418  esmData->counter_2 = 0;
419  esmData->flag_1 = 0;
420  esmData->flag_2 = 1; /* this forces the selection of the transition from IPS to FPS */
421  esmData->logBase = 0;
422 
423  /* Create test SM */
424  smDesc3 = FwSmMakeTestSM3(smData, esmData);
425  if (smDesc3==NULL)
426  return smTestCaseFailure;
427 
428  /* Check configuration of state machine */
429  if (FwSmCheckRec(smDesc3) != smSuccess) {
430  FwSmReleaseRec(smDesc3);
431  return smTestCaseFailure;
432  }
433 
434  /* Start SM and check outcome of start operation */
435  FwSmStart(smDesc3);
436  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
437  FwSmReleaseRec(smDesc3);
438  return smTestCaseFailure;
439  }
440 
441  if ((esmData->counter_1!=0) || (esmData->counter_2!=2) || (FwSmGetCurState(FwSmGetEmbSmCur(smDesc3))!=0)) {
442  FwSmReleaseRec(smDesc3);
443  return smTestCaseFailure;
444  }
445 
446  /* Stop SM and check outcome of stop operation */
447  smDesc2 = FwSmGetEmbSmCur(smDesc3); /* get the SM embedded in the current state of smDesc3 */
448  FwSmStop(smDesc3);
449  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=0)) {
450  FwSmReleaseRec(smDesc3);
451  return smTestCaseFailure;
452  }
453 
454  if ((esmData->counter_1!=0) || (esmData->counter_2!=2) || (FwSmGetCurState(smDesc2)!=0)) {
455  FwSmReleaseRec(smDesc3);
456  return smTestCaseFailure;
457  }
458 
459  FwSmReleaseRec(smDesc3);
460  return smTestCaseSuccess;
461 }
462 
463 /*------------------------------------------------------------------------------------------------- */
465  struct TestSmData sSmData;
466  struct TestSmData* smData = &sSmData;
467  FwSmDesc_t smDesc;
468 
469  /* reset log */
470  fwSm_logIndex = 0;
471 
472  /* Initialize data structure holding the state machine data */
473  smData->counter_1 = 0;
474  smData->counter_2 = 0;
475  smData->flag_1 = 0;
476  smData->flag_2 = 0;
477  smData->logBase = 0;
478 
479  /* Create test SM */
480  smDesc = FwSmMakeTestSM1(smData);
481  if (smDesc==NULL)
482  return smTestCaseFailure;
483 
484  /* Check configuration of state machine */
485  if (FwSmCheck(smDesc) != smSuccess) {
486  FwSmRelease(smDesc);
487  return smTestCaseFailure;
488  }
489 
490  /* Attempt executing a stopped state machine and check that nothing happens */
491  FwSmExecute(smDesc);
492  if ((smData->counter_1!=0) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=0) ||
493  (smData->logBase!=0)) {
494  FwSmReleaseRec(smDesc);
495  return smTestCaseFailure;
496  }
497 
498  /* Start SM (this brings it to state S1) */
499  FwSmStart(smDesc);
500  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
501  FwSmReleaseRec(smDesc);
502  return smTestCaseFailure;
503  }
504 
505  /* Execute state machine twice and check success */
506  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
507  if ((smData->counter_1!=3) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
508  FwSmReleaseRec(smDesc);
509  return smTestCaseFailure;
510  }
511 
512  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
513  if ((smData->counter_1!=5) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
514  FwSmReleaseRec(smDesc);
515  return smTestCaseFailure;
516  }
517 
518  FwSmReleaseRec(smDesc);
519  return smTestCaseSuccess;
520 }
521 
522 /*------------------------------------------------------------------------------------------------- */
524  struct TestSmData sSmData;
525  struct TestSmData* smData = &sSmData;
526  struct TestSmData sEsmData;
527  struct TestSmData* esmData = &sEsmData;
528  FwSmDesc_t smDesc3;
529  FwSmDesc_t smDesc2;
530 
531  /* reset log */
532  fwSm_logIndex = 0;
533 
534  /* Initialize data structure to hold the data of the embedding state machine */
535  smData->counter_1 = 0;
536  smData->counter_2 = 0;
537  smData->flag_1 = 0;
538  smData->flag_2 = 0;
539  smData->logBase = 0;
540 
541  /* Initialize data structure to hold the data of the embedded state machine */
542  esmData->counter_1 = 0;
543  esmData->counter_2 = 0;
544  esmData->flag_1 = 1; /* this forces the selection of the transition from IPS to S1 */
545  esmData->flag_2 = 0;
546  esmData->logBase = 0;
547 
548  /* Create test SM */
549  smDesc3 = FwSmMakeTestSM3(smData, esmData);
550  if (smDesc3==NULL)
551  return smTestCaseFailure;
552 
553  /* Check configuration of state machine */
554  if (FwSmCheckRec(smDesc3) != smSuccess) {
555  FwSmReleaseRec(smDesc3);
556  return smTestCaseFailure;
557  }
558 
559  /* Start SM and check outcome of start operation */
560  FwSmStart(smDesc3);
561  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
562  FwSmReleaseRec(smDesc3);
563  return smTestCaseFailure;
564  }
565 
566  if ((esmData->counter_1!=1) || (esmData->counter_2!=2) || (FwSmGetCurState(FwSmGetEmbSmCur(smDesc3))!=STATE_S1)) {
567  FwSmReleaseRec(smDesc3);
568  return smTestCaseFailure;
569  }
570 
571  /* Execute SM twice and check outcome of Execute operation */
572  smDesc2 = FwSmGetEmbSmCur(smDesc3); /* get the SM embedded in the current state of smDesc3 */
573  FwSmMakeTrans(smDesc3, FW_TR_EXECUTE);
574  if ((smData->counter_1!=3) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
575  FwSmReleaseRec(smDesc3);
576  return smTestCaseFailure;
577  }
578 
579  if ((esmData->counter_1!=3) || (esmData->counter_2!=2) || (FwSmGetCurState(smDesc2)!=STATE_S1)) {
580  FwSmReleaseRec(smDesc3);
581  return smTestCaseFailure;
582  }
583 
584  FwSmMakeTrans(smDesc3, FW_TR_EXECUTE);
585  if ((smData->counter_1!=5) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc3)!=STATE_S1)) {
586  FwSmReleaseRec(smDesc3);
587  return smTestCaseFailure;
588  }
589 
590  if ((esmData->counter_1!=5) || (esmData->counter_2!=2) || (FwSmGetCurState(smDesc2)!=STATE_S1)) {
591  FwSmReleaseRec(smDesc3);
592  return smTestCaseFailure;
593  }
594 
595  FwSmReleaseRec(smDesc3);
596  return smTestCaseSuccess;
597 }
598 
599 /*------------------------------------------------------------------------------------------------- */
601  struct TestSmData sSmData;
602  struct TestSmData* smData = &sSmData;
603  FwSmDesc_t smDesc4;
604 
605  /* reset log */
606  fwSm_logIndex = 0;
607 
608  /* Initialize data structure holding the state machine data */
609  smData->counter_1 = 0;
610  smData->counter_2 = 0;
611  smData->flag_1 = 1; /* Allow transition to take place */
612  smData->flag_2 = 0;
613  smData->logBase = 0;
614 
615  /* Create test SM */
616  smDesc4 = FwSmMakeTestSM4(smData);
617  if (smDesc4==NULL)
618  return smTestCaseFailure;
619 
620  /* Check configuration of state machine */
621  if (FwSmCheck(smDesc4) != smSuccess) {
622  FwSmRelease(smDesc4);
623  return smTestCaseFailure;
624  }
625 
626  /* Start SM (this brings it to state S1) */
627  FwSmStart(smDesc4);
628  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc4)!=STATE_S1)) {
629  FwSmRelease(smDesc4);
630  return smTestCaseFailure;
631  }
632 
633  /* Execute state machine and check success */
634  FwSmMakeTrans(smDesc4, FW_TR_EXECUTE);
635  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc4)!=STATE_S2)) {
636  FwSmRelease(smDesc4);
637  return smTestCaseFailure;
638  }
639 
640  FwSmMakeTrans(smDesc4, FW_TR_EXECUTE);
641  if ((smData->counter_1!=15) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc4)!=STATE_S1)) {
642  FwSmRelease(smDesc4);
643  return smTestCaseFailure;
644  }
645 
646  FwSmRelease(smDesc4);
647  return smTestCaseSuccess;
648 }
649 
650 /*------------------------------------------------------------------------------------------------- */
652  struct TestSmData sSmData;
653  struct TestSmData* smData = &sSmData;
654  FwSmDesc_t smDesc4;
655 
656  /* reset log */
657  fwSm_logIndex = 0;
658 
659  /* Initialize data structure holding the state machine data */
660  smData->counter_1 = 0;
661  smData->counter_2 = 0;
662  smData->flag_1 = 1; /* Allow transition to take place */
663  smData->flag_2 = 0;
664  smData->logBase = 0;
665 
666  /* Create test SM */
667  smDesc4 = FwSmMakeTestSM4(smData);
668  if (smDesc4==NULL)
669  return smTestCaseFailure;
670 
671  /* Check configuration of state machine */
672  if (FwSmCheck(smDesc4) != smSuccess) {
673  FwSmRelease(smDesc4);
674  return smTestCaseFailure;
675  }
676 
677  /* Start SM (this brings it to state S1) */
678  FwSmStart(smDesc4);
679  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc4)!=STATE_S1)) {
680  FwSmRelease(smDesc4);
681  return smTestCaseFailure;
682  }
683 
684  /* Execute state machine to bring it to state S2 */
685  FwSmMakeTrans(smDesc4, FW_TR_EXECUTE);
686  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc4)!=STATE_S2)) {
687  FwSmRelease(smDesc4);
688  return smTestCaseFailure;
689  }
690 
691  /* Execute self-transition */
692  fwSm_logIndex = 0; /* reset log */
693  FwSmMakeTrans(smDesc4, TR4);
694  if ((smData->counter_1!=13) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc4)!=STATE_S2)) {
695  FwSmRelease(smDesc4);
696  return smTestCaseFailure;
697  }
698  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
699  FwSmRelease(smDesc4);
700  return smTestCaseFailure;
701  }
702 
703  FwSmRelease(smDesc4);
704  return smTestCaseSuccess;
705 }
706 
707 /*------------------------------------------------------------------------------------------------- */
709  struct TestSmData sSmData;
710  struct TestSmData* smData = &sSmData;
711  FwSmDesc_t smDesc5;
712 
713  /* reset log */
714  fwSm_logIndex = 0;
715 
716  /* Initialize data structure holding the state machine data */
717  smData->counter_1 = 0;
718  smData->counter_2 = 0;
719  smData->flag_1 = 1; /* allow transition to take place */
720  smData->flag_2 = 0;
721  smData->logBase = 0;
722 
723  /* Create test SM */
724  smDesc5 = FwSmMakeTestSM5(smData);
725  if (smDesc5==NULL)
726  return smTestCaseFailure;
727 
728  /* Check configuration of state machine */
729  if (FwSmCheck(smDesc5) != smSuccess) {
730  FwSmRelease(smDesc5);
731  return smTestCaseFailure;
732  }
733  /* Start SM (this brings it to state S1) */
734  FwSmStart(smDesc5);
735  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1)) {
736  FwSmRelease(smDesc5);
737  return smTestCaseFailure;
738  }
739 
740  /* Send transition command TR4 to SM and check that this has no effect */
741  fwSm_logIndex = 0;
742  FwSmMakeTrans(smDesc5, TR4);
743  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
744  FwSmRelease(smDesc5);
745  return smTestCaseFailure;
746  }
747 
748  /* Set guard to prevent transition TR2 from S1 to S2 and then check that transition does not take place */
749  smData->flag_1 = 0;
750  FwSmMakeTrans(smDesc5, TR2);
751  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
752  FwSmRelease(smDesc5);
753  return smTestCaseFailure;
754  }
755 
756  /* Set guard to allow transition TR2 from S1 to S2 and then check that transition does take place */
757  smData->flag_1 = 1;
758  FwSmMakeTrans(smDesc5, TR2);
759  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=3)) {
760  FwSmRelease(smDesc5);
761  return smTestCaseFailure;
762  }
763  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
764  FwSmRelease(smDesc5);
765  return smTestCaseFailure;
766  }
767 
768  FwSmRelease(smDesc5);
769  return smTestCaseSuccess;
770 }
771 
772 /*------------------------------------------------------------------------------------------------- */
774  struct TestSmData sSmData;
775  struct TestSmData* smData = &sSmData;
776  FwSmDesc_t smDesc5;
777 
778  /* reset log */
779  fwSm_logIndex = 0;
780 
781  /* Initialize data structure holding the state machine data */
782  smData->counter_1 = 0;
783  smData->counter_2 = 0;
784  smData->flag_1 = 1; /* allow transition to take place */
785  smData->flag_2 = 0;
786  smData->logBase = 0;
787 
788  /* Create test SM */
789  smDesc5 = FwSmMakeTestSM5(smData);
790  if (smDesc5==NULL)
791  return smTestCaseFailure;
792 
793  /* Check configuration of state machine */
794  if (FwSmCheck(smDesc5) != smSuccess) {
795  FwSmRelease(smDesc5);
796  return smTestCaseFailure;
797  }
798 
799  /* Start SM (this brings it to state S1) */
800  FwSmStart(smDesc5);
801  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1)) {
802  FwSmRelease(smDesc5);
803  return smTestCaseFailure;
804  }
805 
806  /* Send transition command TR2 to SM (this brings it to state S2) */
807  FwSmMakeTrans(smDesc5, TR2);
808  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc5)!=STATE_S2)) {
809  FwSmRelease(smDesc5);
810  return smTestCaseFailure;
811  }
812 
813  /* Set guards to open transition from S2 to S1 and then perform transition */
814  smData->flag_1 = 1;
815  smData->flag_2 = 0;
816  fwSm_logIndex = 0;
817  FwSmMakeTrans(smDesc5, TR6);
818  if ((smData->counter_1!=11) || (smData->counter_2!=4) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=4)) {
819  FwSmRelease(smDesc5);
820  return smTestCaseFailure;
821  }
822  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=4) || (fwSm_logMarker[3]!=1)) {
823  FwSmRelease(smDesc5);
824  return smTestCaseFailure;
825  }
826  if ((fwSm_logState[0]!=2) || (fwSm_logState[1]!=2) || (fwSm_logState[2]!=2) || (fwSm_logState[3]!=1)) {
827  FwSmRelease(smDesc5);
828  return smTestCaseFailure;
829  }
830 
831  /* Send transition command TR2 to SM (this brings it to state S2) */
832  FwSmMakeTrans(smDesc5, TR2);
833  if ((smData->counter_1!=16) || (smData->counter_2!=5) || (FwSmGetCurState(smDesc5)!=STATE_S2)) {
834  FwSmRelease(smDesc5);
835  return smTestCaseFailure;
836  }
837 
838  /* Set guards to open transition from S2 back to S2 and then perform transition */
839  smData->flag_1 = 0;
840  smData->flag_2 = 1;
841  fwSm_logIndex = 0;
842  FwSmMakeTrans(smDesc5, TR6);
843  if ((smData->counter_1!=21) || (smData->counter_2!=7) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=4)) {
844  FwSmRelease(smDesc5);
845  return smTestCaseFailure;
846  }
847  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=4) || (fwSm_logMarker[3]!=1)) {
848  FwSmRelease(smDesc5);
849  return smTestCaseFailure;
850  }
851  if ((fwSm_logState[0]!=2) || (fwSm_logState[1]!=2) || (fwSm_logState[2]!=2) || (fwSm_logState[3]!=2)) {
852  FwSmRelease(smDesc5);
853  return smTestCaseFailure;
854  }
855 
856  FwSmRelease(smDesc5);
857  return smTestCaseSuccess;
858 }
859 
860 /*------------------------------------------------------------------------------------------------- */
862  struct TestSmData sSmData;
863  struct TestSmData* smData = &sSmData;
864  struct TestSmData sEsmData;
865  struct TestSmData* esmData = &sEsmData;
866  FwSmDesc_t smDesc6;
867 
868  /* reset log */
869  fwSm_logIndex = 0;
870 
871  /* Initialize data structure to hold the data of the embedding state machine */
872  smData->counter_1 = 0;
873  smData->counter_2 = 0;
874  smData->flag_1 = 1; /* this allows all transitions in embedding SM */
875  smData->flag_2 = 0;
876  smData->logBase = 0;
877 
878  /* Initialize data structure to hold the data of the embedded state machine */
879  esmData->counter_1 = 0;
880  esmData->counter_2 = 0;
881  esmData->flag_1 = 1; /* this forces the selection of the transition from S2 to S1 in ESM */
882  esmData->flag_2 = 0;
883  esmData->logBase = 10;
884 
885  /* Create test SM */
886  smDesc6 = FwSmMakeTestSM6(smData, esmData);
887  if (smDesc6==NULL)
888  return smTestCaseFailure;
889 
890  /* Check configuration of state machine */
891  if (FwSmCheckRec(smDesc6) != smSuccess) {
892  FwSmReleaseRec(smDesc6);
893  return smTestCaseFailure;
894  }
895 
896  /* Start SM and check outcome of start operation */
897  fwSm_logIndex = 0; /* reset log */
898  FwSmStart(smDesc6);
899  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc6)!=1)) {
900  FwSmReleaseRec(smDesc6);
901  return smTestCaseFailure;
902  }
903  if ((esmData->counter_1!=0) || (esmData->counter_2!=0) || (FwSmGetCurState(FwSmGetEmbSm(smDesc6, STATE_S2))!=0)) {
904  FwSmReleaseRec(smDesc6);
905  return smTestCaseFailure;
906  }
907  if ((fwSm_logMarker[0]!=4) || (fwSm_logMarker[1]!=1)) {
908  FwSmReleaseRec(smDesc6);
909  return smTestCaseFailure;
910  }
911  if ((fwSm_logState[0]!=0) || (fwSm_logState[1]!=1)) {
912  FwSmReleaseRec(smDesc6);
913  return smTestCaseFailure;
914  }
915 
916  /* Execute SM (this causes a transition from S1 to S2 and the starting of the ESM) */
917  FwSmMakeTrans(smDesc6, FW_TR_EXECUTE);
918  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
919  FwSmReleaseRec(smDesc6);
920  return smTestCaseFailure;
921  }
922  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S1)) {
923  FwSmReleaseRec(smDesc6);
924  return smTestCaseFailure;
925  }
926  if ((fwSm_logMarker[2]!=2) || (fwSm_logMarker[3]!=3) || (fwSm_logMarker[4]!=4) || (fwSm_logMarker[5]!=1)) {
927  FwSmReleaseRec(smDesc6);
928  return smTestCaseFailure;
929  }
930  if ((fwSm_logState[2]!=1) || (fwSm_logState[3]!=1) || (fwSm_logState[4]!=1) || (fwSm_logState[5]!=2)) {
931  FwSmReleaseRec(smDesc6);
932  return smTestCaseFailure;
933  }
934  if ((fwSm_logMarker[6]!=14) || (fwSm_logMarker[7]!=11)) {
935  FwSmReleaseRec(smDesc6);
936  return smTestCaseFailure;
937  }
938  if ((fwSm_logState[6]!=10) || (fwSm_logState[7]!=11)) {
939  FwSmReleaseRec(smDesc6);
940  return smTestCaseFailure;
941  }
942 
943  /* Send TR5 command to SM (this has no effect on either the SM or its ESM) */
944  FwSmMakeTrans(smDesc6, TR5);
945  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
946  FwSmReleaseRec(smDesc6);
947  return smTestCaseFailure;
948  }
949  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S1)) {
950  FwSmReleaseRec(smDesc6);
951  return smTestCaseFailure;
952  }
953  if (fwSm_logIndex!=8) {
954  FwSmReleaseRec(smDesc6);
955  return smTestCaseFailure;
956  }
957 
958  /* Send TR2 command to SM (this has no effect on the SM but causes the ESM to go from S1 to S2) */
959  FwSmMakeTrans(smDesc6, TR2);
960  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
961  FwSmReleaseRec(smDesc6);
962  return smTestCaseFailure;
963  }
964  if ((esmData->counter_1!=6) || (esmData->counter_2!=2) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S2)) {
965  FwSmReleaseRec(smDesc6);
966  return smTestCaseFailure;
967  }
968  if (fwSm_logIndex!=11) {
969  FwSmReleaseRec(smDesc6);
970  return smTestCaseFailure;
971  }
972  if ((fwSm_logMarker[8]!=13) || (fwSm_logMarker[9]!=14) || (fwSm_logMarker[10]!=11)) {
973  FwSmReleaseRec(smDesc6);
974  return smTestCaseFailure;
975  }
976  if ((fwSm_logState[8]!=11) || (fwSm_logState[9]!=11) || (fwSm_logState[10]!=12)) {
977  FwSmReleaseRec(smDesc6);
978  return smTestCaseFailure;
979  }
980 
981  FwSmReleaseRec(smDesc6);
982  return smTestCaseSuccess;
983 }
984 
985 /*------------------------------------------------------------------------------------------------- */
987  struct TestSmData sSmData;
988  struct TestSmData* smData = &sSmData;
989  struct TestSmData sEsmData;
990  struct TestSmData* esmData = &sEsmData;
991  FwSmDesc_t smDesc6;
992 
993  /* reset log */
994  fwSm_logIndex = 0;
995 
996  /* Initialize data structure to hold the data of the embedding state machine */
997  smData->counter_1 = 0;
998  smData->counter_2 = 0;
999  smData->flag_1 = 1; /* this allows all transitions in embedding SM */
1000  smData->flag_2 = 0;
1001  smData->logBase = 0;
1002 
1003  /* Initialize data structure to hold the data of the embedded state machine */
1004  esmData->counter_1 = 0;
1005  esmData->counter_2 = 0;
1006  esmData->flag_1 = 1; /* this forces the selection of the transition from S2 to S1 in ESM */
1007  esmData->flag_2 = 0;
1008  esmData->logBase = 10;
1009 
1010  /* Create test SM */
1011  smDesc6 = FwSmMakeTestSM6(smData, esmData);
1012  if (smDesc6==NULL)
1013  return smTestCaseFailure;
1014 
1015  /* Check configuration of state machine */
1016  if (FwSmCheckRec(smDesc6) != smSuccess) {
1017  FwSmReleaseRec(smDesc6);
1018  return smTestCaseFailure;
1019  }
1020 
1021  /* Start and execute SM (this brings the embedding SM in S2 and starts the ESM) */
1022  fwSm_logIndex = 0; /* reset log */
1023  FwSmStart(smDesc6);
1024  FwSmExecute(smDesc6);
1025  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
1026  FwSmReleaseRec(smDesc6);
1027  return smTestCaseFailure;
1028  }
1029  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S1)) {
1030  FwSmReleaseRec(smDesc6);
1031  return smTestCaseFailure;
1032  }
1033 
1034  /* Send TR2 command to SM (this has no effect on the SM but causes the ESM to go from S1 to S2) */
1035  FwSmMakeTrans(smDesc6, TR2);
1036  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
1037  FwSmReleaseRec(smDesc6);
1038  return smTestCaseFailure;
1039  }
1040  if ((esmData->counter_1!=6) || (esmData->counter_2!=2) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S2)) {
1041  FwSmReleaseRec(smDesc6);
1042  return smTestCaseFailure;
1043  }
1044  fwSm_logIndex = 0;
1045 
1046  /* Execute the SM (this causes the do-action of the S2 of both the SM and ESM to be executed and then triggers */
1047  /* a transition from S2 to S1 in the SM) */
1048  FwSmExecute(smDesc6);
1049  if ((smData->counter_1!=15) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc6)!=STATE_S1)) {
1050  FwSmReleaseRec(smDesc6);
1051  return smTestCaseFailure;
1052  }
1053  if ((esmData->counter_1!=12) || (esmData->counter_2!=2) || (FwSmGetCurState(FwSmGetEmbSm(smDesc6, STATE_S2))!=0)) {
1054  FwSmReleaseRec(smDesc6);
1055  return smTestCaseFailure;
1056  }
1057  if (fwSm_logIndex!=6) {
1058  FwSmReleaseRec(smDesc6);
1059  return smTestCaseFailure;
1060  }
1061  if ((fwSm_logMarker[0]!=2) || (fwSm_logMarker[1]!=12)|| (fwSm_logMarker[2]!=13) || (fwSm_logMarker[3]!=3) ||
1062  (fwSm_logMarker[4]!=4) || (fwSm_logMarker[5]!=1)) {
1063  FwSmReleaseRec(smDesc6);
1064  return smTestCaseFailure;
1065  }
1066  if ((fwSm_logState[0]!=2) || (fwSm_logState[1]!=12)|| (fwSm_logState[2]!=12) ||
1067  (fwSm_logState[3]!=2) || (fwSm_logState[4]!=2) || (fwSm_logState[5]!=1)) {
1068  FwSmReleaseRec(smDesc6);
1069  return smTestCaseFailure;
1070  }
1071 
1072  FwSmReleaseRec(smDesc6);
1073  return smTestCaseSuccess;
1074 }
1075 
1076 /*------------------------------------------------------------------------------------------------- */
1078  struct TestSmData sSmData;
1079  struct TestSmData* smData = &sSmData;
1080  struct TestSmData sEsmData;
1081  struct TestSmData* esmData = &sEsmData;
1082  FwSmDesc_t smDesc6;
1083 
1084  /* reset log */
1085  fwSm_logIndex = 0;
1086 
1087  /* Initialize data structure to hold the data of the embedding state machine */
1088  smData->counter_1 = 0;
1089  smData->counter_2 = 0;
1090  smData->flag_1 = 1; /* this allows all transitions in embedding SM */
1091  smData->flag_2 = 0;
1092  smData->logBase = 0;
1093 
1094  /* Initialize data structure to hold the data of the embedded state machine */
1095  esmData->counter_1 = 0;
1096  esmData->counter_2 = 0;
1097  esmData->flag_1 = 1; /* this forces the selection of the transition from S2 to S1 in ESM */
1098  esmData->flag_2 = 0;
1099  esmData->logBase = 10;
1100 
1101  /* Create test SM */
1102  smDesc6 = FwSmMakeTestSM6(smData, esmData);
1103  if (smDesc6==NULL)
1104  return smTestCaseFailure;
1105 
1106  /* Check configuration of state machine */
1107  if (FwSmCheckRec(smDesc6) != smSuccess) {
1108  FwSmReleaseRec(smDesc6);
1109  return smTestCaseFailure;
1110  }
1111 
1112  /* Start and execute SM (this brings the embedding SM in S2 and starts the ESM) */
1113  fwSm_logIndex = 0; /* reset log */
1114  FwSmStart(smDesc6);
1115  FwSmExecute(smDesc6);
1116  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
1117  FwSmReleaseRec(smDesc6);
1118  return smTestCaseFailure;
1119  }
1120  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S1)) {
1121  FwSmReleaseRec(smDesc6);
1122  return smTestCaseFailure;
1123  }
1124 
1125  /* Send TR2 command to SM (this has no effect on the SM but causes the ESM to go from S1 to S2) */
1126  FwSmMakeTrans(smDesc6, TR2);
1127  if ((smData->counter_1!=8) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
1128  FwSmReleaseRec(smDesc6);
1129  return smTestCaseFailure;
1130  }
1131  if ((esmData->counter_1!=6) || (esmData->counter_2!=2) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S2)) {
1132  FwSmReleaseRec(smDesc6);
1133  return smTestCaseFailure;
1134  }
1135 
1136  /* Send TR4 command to SM (this causes a self-transition on both the SM and the ESM) */
1137  fwSm_logIndex = 0; /* reset log counter */
1138  FwSmMakeTrans(smDesc6, TR4);
1139  if ((smData->counter_1!=13) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc6)!=STATE_S2)) {
1140  FwSmReleaseRec(smDesc6);
1141  return smTestCaseFailure;
1142  }
1143  if ((esmData->counter_1!=16) || (esmData->counter_2!=4) || (FwSmGetCurStateEmb(smDesc6)!=STATE_S1)) {
1144  FwSmReleaseRec(smDesc6);
1145  return smTestCaseFailure;
1146  }
1147  if (fwSm_logIndex!=9) {
1148  FwSmReleaseRec(smDesc6);
1149  return smTestCaseFailure;
1150  }
1151  if ((fwSm_logMarker[0]!=13) || (fwSm_logMarker[1]!=14) || (fwSm_logMarker[2]!=11) || (fwSm_logMarker[3]!=13) ||
1152  (fwSm_logMarker[4]!=3)) {
1153  FwSmReleaseRec(smDesc6);
1154  return smTestCaseFailure;
1155  }
1156  if ((fwSm_logMarker[5]!=4) || (fwSm_logMarker[6]!=1) || (fwSm_logMarker[7]!=14) || (fwSm_logMarker[8]!=11)) {
1157  FwSmReleaseRec(smDesc6);
1158  return smTestCaseFailure;
1159  }
1160  if ((fwSm_logState[0]!=12) || (fwSm_logState[1]!=12) || (fwSm_logState[2]!=12)|| (fwSm_logState[3]!=12) ||
1161  (fwSm_logState[4]!=2)) {
1162  FwSmReleaseRec(smDesc6);
1163  return smTestCaseFailure;
1164  }
1165  if ((fwSm_logState[5]!=2) || (fwSm_logState[6]!=2) || (fwSm_logState[7]!=10) || (fwSm_logState[8]!=11)) {
1166  FwSmReleaseRec(smDesc6);
1167  return smTestCaseFailure;
1168  }
1169 
1170  FwSmReleaseRec(smDesc6);
1171  return smTestCaseSuccess;
1172 }
1173 
1174 /*------------------------------------------------------------------------------------------------- */
1176  struct TestSmData sSmData;
1177  struct TestSmData* smData = &sSmData;
1178  FwSmDesc_t smDesc5;
1179 
1180  /* reset log */
1181  fwSm_logIndex = 0;
1182 
1183  /* Initialize data structure holding the state machine data */
1184  smData->counter_1 = 0;
1185  smData->counter_2 = 0;
1186  smData->flag_1 = 1; /* allow transition to take place */
1187  smData->flag_2 = 0;
1188  smData->logBase = 0;
1189 
1190  /* Create test SM */
1191  smDesc5 = FwSmMakeTestSM5Dir(smData);
1192 
1193  /* Check configuration of state machine */
1194  if (FwSmCheck(smDesc5) != smSuccess) {
1195  return smTestCaseFailure;
1196  }
1197 
1198  /* Start SM (this brings it to state S1) */
1199  FwSmStart(smDesc5);
1200  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1)) {
1201  return smTestCaseFailure;
1202  }
1203 
1204  /* Send transition command TR4 to SM and check that this has no effect */
1205  fwSm_logIndex = 0;
1206  FwSmMakeTrans(smDesc5, TR4);
1207  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
1208  return smTestCaseFailure;
1209  }
1210 
1211  /* Set guard to prevent transition TR2 from S1 to S2 and then check that transition does not take place */
1212  smData->flag_1 = 0;
1213  FwSmMakeTrans(smDesc5, TR2);
1214  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
1215  return smTestCaseFailure;
1216  }
1217 
1218  /* Set guard to allow transition TR2 from S1 to S2 and then check that transition does take place */
1219  smData->flag_1 = 1;
1220  FwSmMakeTrans(smDesc5, TR2);
1221  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=3)) {
1222  return smTestCaseFailure;
1223  }
1224  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
1225  return smTestCaseFailure;
1226  }
1227 
1228  /* Set guard to allow transition from CPS1 to S2 and then trigger transition from S2 back to S2 via CPS1 */
1229  smData->flag_1 = 0;
1230  smData->flag_2 = 1;
1231  fwSm_logIndex = 0;
1232  FwSmMakeTrans(smDesc5, TR6);
1233  if ((smData->counter_1!=11) || (smData->counter_2!=4) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=4)) {
1234  return smTestCaseFailure;
1235  }
1236 
1237  /* Set guard to allow transition from S2 to FPS and then trigger transition */
1238  smData->flag_1 = 1;
1239  fwSm_logIndex = 0;
1240  FwSmMakeTrans(smDesc5, TR5);
1241  if ((smData->counter_1!=15) || (smData->counter_2!=5) || (FwSmGetCurState(smDesc5)!=0) || (fwSm_logIndex!=2)) {
1242  return smTestCaseFailure;
1243  }
1244 
1245  return smTestCaseSuccess;
1246 }
1247 
1248 
1249 /*------------------------------------------------------------------------------------------------- */
1251  struct TestSmData sSmData;
1252  struct TestSmData* smData = &sSmData;
1253  FwSmDesc_t smDesc5;
1254 
1255  /* reset log */
1256  fwSm_logIndex = 0;
1257 
1258  /* Initialize data structure holding the state machine data */
1259  smData->counter_1 = 0;
1260  smData->counter_2 = 0;
1261  smData->flag_1 = 1; /* allow transition to take place */
1262  smData->flag_2 = 0;
1263  smData->logBase = 0;
1264 
1265  /* Create test SM */
1266  smDesc5 = FwSmMakeTestSM5Static(smData);
1267 
1268  /* Check configuration of state machine */
1269  if (FwSmCheck(smDesc5) != smSuccess) {
1270  return smTestCaseFailure;
1271  }
1272 
1273  /* Start SM (this brings it to state S1) */
1274  FwSmStart(smDesc5);
1275  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1)) {
1276  return smTestCaseFailure;
1277  }
1278 
1279  /* Send transition command TR4 to SM and check that this has no effect */
1280  fwSm_logIndex = 0;
1281  FwSmMakeTrans(smDesc5, TR4);
1282  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
1283  return smTestCaseFailure;
1284  }
1285 
1286  /* Set guard to prevent transition TR2 from S1 to S2 and then check that transition does not take place */
1287  smData->flag_1 = 0;
1288  FwSmMakeTrans(smDesc5, TR2);
1289  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc5)!=STATE_S1) || (fwSm_logIndex!=0)) {
1290  return smTestCaseFailure;
1291  }
1292 
1293  /* Set guard to allow transition TR2 from S1 to S2 and then check that transition does take place */
1294  smData->flag_1 = 1;
1295  FwSmMakeTrans(smDesc5, TR2);
1296  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=3)) {
1297  return smTestCaseFailure;
1298  }
1299  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
1300  return smTestCaseFailure;
1301  }
1302 
1303  /* Set guard to allow transition from CPS1 to S2 and then trigger transition from S2 back to S2 via CPS1 */
1304  smData->flag_1 = 0;
1305  smData->flag_2 = 1;
1306  fwSm_logIndex = 0;
1307  FwSmMakeTrans(smDesc5, TR6);
1308  if ((smData->counter_1!=11) || (smData->counter_2!=4) || (FwSmGetCurState(smDesc5)!=STATE_S2) || (fwSm_logIndex!=4)) {
1309  return smTestCaseFailure;
1310  }
1311 
1312  /* Set guard to allow transition from S2 to FPS and then trigger transition */
1313  smData->flag_1 = 1;
1314  fwSm_logIndex = 0;
1315  FwSmMakeTrans(smDesc5, TR5);
1316  if ((smData->counter_1!=15) || (smData->counter_2!=5) || (FwSmGetCurState(smDesc5)!=0) || (fwSm_logIndex!=2)) {
1317  return smTestCaseFailure;
1318  }
1319 
1320  return smTestCaseSuccess;
1321 }
1322 
1323 /*------------------------------------------------------------------------------------------------- */
1325  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1326  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1327  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
1328  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1329  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1330  FwSmDesc_t smDesc;
1331 
1332  /* Create a state machine with one state, one CPS, and four transitions */
1333  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1334  FwSmSetData(smDesc, NULL);
1335 
1336  /* Attempt to add a state with a negative number of out-going transitions */
1337  FwSmAddState(smDesc, STATE_S1, -1, NULL, NULL, NULL, NULL);
1338  if (FwSmGetErrCode(smDesc) != smNegOutTrans) {
1339  FwSmRelease(smDesc);
1340  return smTestCaseFailure;
1341  }
1342 
1343  /* Attempt to add the same state twice and check that an error is returned */
1344  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1345  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1346  if (FwSmGetErrCode(smDesc) != smStateIdInUse) {
1347  FwSmRelease(smDesc);
1348  return smTestCaseFailure;
1349  }
1350 
1351  /* Attempt to add a state with an illegal identifier */
1352  FwSmAddState(smDesc, 0, 1, NULL, NULL, NULL, NULL);
1353  if (FwSmGetErrCode(smDesc) != smIllStateId) {
1354  FwSmRelease(smDesc);
1355  return smTestCaseFailure;
1356  }
1357  FwSmAddState(smDesc, 2, 1, NULL, NULL, NULL, NULL);
1358  if (FwSmGetErrCode(smDesc) != smIllStateId) {
1359  FwSmRelease(smDesc);
1360  return smTestCaseFailure;
1361  }
1362 
1363  /* Attempt to add the same choice pseudo-state twice and check that an error is returned */
1364  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1365  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1366  if (FwSmGetErrCode(smDesc) != smChoiceIdInUse) {
1367  FwSmRelease(smDesc);
1368  return smTestCaseFailure;
1369  }
1370 
1371  /* Attempt to add a choice pseudo-state with an illegal identifier */
1372  FwSmAddChoicePseudoState(smDesc, 0, 2);
1373  if (FwSmGetErrCode(smDesc) != smIllChoiceId) {
1374  FwSmRelease(smDesc);
1375  return smTestCaseFailure;
1376  }
1377  FwSmAddChoicePseudoState(smDesc, 2, 2);
1378  if (FwSmGetErrCode(smDesc) != smIllChoiceId) {
1379  FwSmRelease(smDesc);
1380  return smTestCaseFailure;
1381  }
1382 
1383  /* Attempt to add too many transitions and check that an error is returned */
1384  FwSmAddTransStaToSta(smDesc, TR1, STATE_S1, STATE_S1, NULL, NULL);
1385  if (FwSmGetErrCode(smDesc) != smIllChoiceId) {
1386  FwSmRelease(smDesc);
1387  return smTestCaseFailure;
1388  }
1389  FwSmAddTransStaToSta(smDesc, TR1, STATE_S1, STATE_S1, NULL, NULL);
1390  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
1391  FwSmRelease(smDesc);
1392  return smTestCaseFailure;
1393  }
1394 
1395  /* Attempt to add the initial transition twice and check that an error is returned */
1396  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
1397  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
1398  FwSmRelease(smDesc);
1399  return smTestCaseFailure;
1400  }
1401  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
1402  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
1403  FwSmRelease(smDesc);
1404  return smTestCaseFailure;
1405  }
1406 
1407  FwSmRelease(smDesc);
1408  return smTestCaseSuccess;
1409 }
1410 
1411 /*------------------------------------------------------------------------------------------------- */
1413  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1414  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1415  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
1416  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1417  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1418  FwSmDesc_t smDesc;
1419 
1420  /* Create a state machine with one state, one CPS, and three transitions */
1421  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1422  FwSmSetData(smDesc, NULL);
1423 
1424  /* Configure state machine without defining the state */
1425  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1426  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1427  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1428  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1429 
1430  /* Check state machine and verify that an error is reported */
1431  if (FwSmCheck(smDesc) != smNullPState) {
1432  FwSmRelease(smDesc);
1433  return smTestCaseFailure;
1434  }
1435  if (FwSmGetErrCode(smDesc) != smSuccess) {
1436  FwSmRelease(smDesc);
1437  return smTestCaseFailure;
1438  }
1439 
1440  FwSmRelease(smDesc);
1441  return smTestCaseSuccess;
1442 }
1443 
1444 /*------------------------------------------------------------------------------------------------- */
1446  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1447  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1448  const FwSmCounterS1_t nOfTrans = 2; /* number of transitions */
1449  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1450  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1451  FwSmDesc_t smDesc;
1452 
1453  /* Create a state machine with one state, one CPS, and two transitions */
1454  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1455  FwSmSetData(smDesc, NULL);
1456 
1457  /* Configure state machine without defining the CPS */
1458  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1459  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
1460  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1461 
1462  /* Check state machine and verify that an error is reported */
1463  if (FwSmCheck(smDesc) != smNullCState) {
1464  FwSmRelease(smDesc);
1465  return smTestCaseFailure;
1466  }
1467  if (FwSmGetErrCode(smDesc) != smSuccess) {
1468  FwSmRelease(smDesc);
1469  return smTestCaseFailure;
1470  }
1471 
1472  FwSmRelease(smDesc);
1473  return smTestCaseSuccess;
1474 }
1475 
1476 /*------------------------------------------------------------------------------------------------- */
1478  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1479  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1480  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
1481  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1482  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1483  FwSmDesc_t smDesc;
1484 
1485  /* Create a state machine with one state, one CPS, and three transitions */
1486  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1487  FwSmSetData(smDesc, NULL);
1488 
1489  /* Configure state machine without defining one of the transitions */
1490  FwSmAddState(smDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
1491  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1492  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1493  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
1494 
1495  /* Check state machine and verify that an error is reported */
1496  if (FwSmCheck(smDesc) != smNullTrans) {
1497  FwSmRelease(smDesc);
1498  return smTestCaseFailure;
1499  }
1500  if (FwSmGetErrCode(smDesc) != smSuccess) {
1501  FwSmRelease(smDesc);
1502  return smTestCaseFailure;
1503  }
1504 
1505  FwSmRelease(smDesc);
1506  return smTestCaseSuccess;
1507 }
1508 
1509 /*------------------------------------------------------------------------------------------------- */
1511  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1512  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1513  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
1514  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1515  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1516  FwSmDesc_t smDesc;
1517 
1518  /* Create a state machine with one state, one CPS, and three transitions */
1519  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1520  FwSmSetData(smDesc, NULL);
1521 
1522  /* Configure state machine without defining the initial transition */
1523  FwSmAddState(smDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
1524  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1525  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1526  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
1527 
1528  /* Check state machine and verify that an error is reported */
1529  if (FwSmCheck(smDesc) != smNullTrans) {
1530  FwSmRelease(smDesc);
1531  return smTestCaseFailure;
1532  }
1533  if (FwSmGetErrCode(smDesc) != smSuccess) {
1534  FwSmRelease(smDesc);
1535  return smTestCaseFailure;
1536  }
1537 
1538  FwSmRelease(smDesc);
1539  return smTestCaseSuccess;
1540 }
1541 
1542 /*------------------------------------------------------------------------------------------------- */
1544  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1545  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
1546  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
1547  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1548  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1549  FwSmDesc_t smDesc;
1550 
1551  /* Create a state machine with one state, no CPS, and three transitions */
1552  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1553  FwSmSetData(smDesc, NULL);
1554 
1555  /* Configure state machine with an extra transition out of S1 */
1556  FwSmAddState(smDesc, STATE_S1, 2, NULL, NULL, NULL, NULL);
1557  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
1558  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1559 
1560  /* Check state machine and verify that an error is reported */
1561  if (FwSmCheck(smDesc) != smNullTrans) {
1562  FwSmRelease(smDesc);
1563  return smTestCaseFailure;
1564  }
1565  if (FwSmGetErrCode(smDesc) != smSuccess) {
1566  FwSmRelease(smDesc);
1567  return smTestCaseFailure;
1568  }
1569 
1570  FwSmRelease(smDesc);
1571  return smTestCaseSuccess;
1572 }
1573 
1574 /*------------------------------------------------------------------------------------------------- */
1576  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1577  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1578  const FwSmCounterS1_t nOfTrans = 5; /* number of transitions */
1579  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1580  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1581  FwSmDesc_t smDesc;
1582 
1583  /* Create a state machine with one state, one CPS, and five transitions */
1584  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1585  FwSmSetData(smDesc, NULL);
1586 
1587  /* Configure state machine with an extra transition out of CPS */
1588  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1589  FwSmAddChoicePseudoState(smDesc, CPS1, 3);
1590  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1591  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
1592  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1593  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1594 
1595  /* Check state machine and verify that an error is reported */
1596  if (FwSmCheck(smDesc) != smNullTrans) {
1597  FwSmRelease(smDesc);
1598  return smTestCaseFailure;
1599  }
1600  if (FwSmGetErrCode(smDesc) != smSuccess) {
1601  FwSmRelease(smDesc);
1602  return smTestCaseFailure;
1603  }
1604 
1605  FwSmRelease(smDesc);
1606  return smTestCaseSuccess;
1607 }
1608 
1609 /*------------------------------------------------------------------------------------------------- */
1611  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1612  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1613  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
1614  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1615  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1616  FwSmDesc_t smDesc;
1617 
1618  /* Create a state machine with one state, one CPS, and four transitions */
1619  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1620  FwSmSetData(smDesc, NULL);
1621 
1622  /* Configure state machine - state S1 has no out-going transitions */
1623  FwSmAddState(smDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
1624  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1625  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1626  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
1627  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1628 
1629  /* Check state machine and verify that an error is reported */
1630  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1631  if (FwSmGetErrCode(smDesc) != smIllTransSrc) {
1632  FwSmRelease(smDesc);
1633  return smTestCaseFailure;
1634  }
1635 
1636  FwSmRelease(smDesc);
1637  return smTestCaseSuccess;
1638 }
1639 
1640 /*------------------------------------------------------------------------------------------------- */
1642  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1643  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1644  const FwSmCounterS1_t nOfTrans = 5; /* number of transitions */
1645  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1646  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1647  FwSmDesc_t smDesc;
1648 
1649  /* Create a state machine with one state, one CPS, and five transitions */
1650  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1651  FwSmSetData(smDesc, NULL);
1652 
1653  /* Configure state machine - CPS1 has only two out-going transitions */
1654  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1655  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1656  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1657  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
1658  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1659  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL); /* Two identical transitions from CPS1 to FPS */
1660  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1661 
1662  /* Check state machine and verify that an error is reported */
1663  if (FwSmCheck(smDesc) != smConfigErr) {
1664  FwSmRelease(smDesc);
1665  return smTestCaseFailure;
1666  }
1667  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
1668  FwSmRelease(smDesc);
1669  return smTestCaseFailure;
1670  }
1671 
1672  FwSmRelease(smDesc);
1673  return smTestCaseSuccess;
1674 }
1675 
1676 /*------------------------------------------------------------------------------------------------- */
1678  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1679  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
1680  const FwSmCounterS1_t nOfTrans = 2; /* number of transitions */
1681  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1682  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1683  FwSmDesc_t smDesc;
1684  FwSmDesc_t esmDesc;
1685 
1686  /* Create a state machine with a missing transition */
1687  esmDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1688  FwSmSetData(esmDesc, NULL);
1689 
1690  FwSmAddState(esmDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
1691  FwSmAddTransIpsToSta(esmDesc, STATE_S1, NULL);
1692 
1693  /* Create a state machine embedding the previous state machine */
1694  smDesc = FwSmCreate(1, 0, 2, 0, 0);
1695  FwSmSetData(smDesc, NULL);
1696 
1697  /* Configure state machine */
1698  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, esmDesc);
1699  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
1700  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1701 
1702  /* Check outer state machine and verify that no error is reported */
1703  if (FwSmCheck(smDesc) != smSuccess) {
1704  FwSmReleaseRec(smDesc);
1705  return smTestCaseFailure;
1706  }
1707  if (FwSmGetErrCode(smDesc) != smSuccess) {
1708  FwSmRelease(smDesc);
1709  return smTestCaseFailure;
1710  }
1711 
1712  /* Check outer state machine recursively and verify that error is reported */
1713  if (FwSmCheckRec(smDesc) != smNullTrans) {
1714  FwSmReleaseRec(smDesc);
1715  return smTestCaseFailure;
1716  }
1717  if (FwSmGetErrCode(smDesc) != smSuccess) {
1718  FwSmRelease(smDesc);
1719  return smTestCaseFailure;
1720  }
1721 
1722  FwSmReleaseRec(smDesc);
1723  return smTestCaseSuccess;
1724 }
1725 
1726 /*------------------------------------------------------------------------------------------------- */
1728  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1729  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1730  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
1731  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1732  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1733  FwSmDesc_t smDesc;
1734 
1735  /* Create a state machine with one state, one CPS, and four transitions */
1736  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1737  FwSmSetData(smDesc, NULL);
1738 
1739  /* Configure state machine - one transition has an illegal destination */
1740  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
1741  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
1742  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
1743  FwSmAddTransCpsToSta(smDesc, CPS1, 3, NULL, NULL); /* illegal destination */
1744  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
1745  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
1746 
1747  /* Check state machine and verify that an error is reported */
1748  if (FwSmCheck(smDesc) != smIllegalPDest) {
1749  FwSmRelease(smDesc);
1750  return smTestCaseFailure;
1751  }
1752  if (FwSmGetErrCode(smDesc) != smSuccess) {
1753  FwSmRelease(smDesc);
1754  return smTestCaseFailure;
1755  }
1756 
1757  FwSmRelease(smDesc);
1758  return smTestCaseSuccess;
1759 }
1760 
1761 /*------------------------------------------------------------------------------------------------- */
1763  struct TestSmData sSmData;
1764  struct TestSmData* smData = &sSmData;
1765  FwSmDesc_t smDesc;
1766 
1767  /* reset log */
1768  fwSm_logIndex = 0;
1769 
1770  /* Initialize data structure to hold the data of the embedding state machine */
1771  smData->counter_1 = 0;
1772  smData->counter_2 = 0;
1773  smData->flag_1 = 0;
1774  smData->flag_2 = 1; /* this allows transition from CPS to FPS */
1775  smData->logBase = 0;
1776 
1777  /* Create test SM */
1778  smDesc = FwSmMakeTestSM7(smData);
1779  if (smDesc==NULL)
1780  return smTestCaseFailure;
1781 
1782  /* Check configuration of state machine */
1783  if (FwSmCheckRec(smDesc) != smSuccess) {
1784  FwSmReleaseRec(smDesc);
1785  return smTestCaseFailure;
1786  }
1787 
1788  /* Start SM (this brings it to S1 */
1789  fwSm_logIndex = 0; /* reset log */
1790  FwSmStart(smDesc);
1791  if ((smData->counter_1!=0) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
1792  FwSmReleaseRec(smDesc);
1793  return smTestCaseFailure;
1794  }
1795  if (fwSm_logIndex!=1) {
1796  FwSmReleaseRec(smDesc);
1797  return smTestCaseFailure;
1798  }
1799 
1800  /* Send TR1 command to SM (this brings it to the FPS via CPS1) */
1801  FwSmMakeTrans(smDesc, TR1);
1802  if ((smData->counter_1!=4) || (smData->counter_2!=3) || (FwSmIsStarted(smDesc)!=0)) {
1803  FwSmReleaseRec(smDesc);
1804  return smTestCaseFailure;
1805  }
1806  if (fwSm_logIndex!=4) {
1807  FwSmReleaseRec(smDesc);
1808  return smTestCaseFailure;
1809  }
1810 
1811  FwSmReleaseRec(smDesc);
1812  return smTestCaseSuccess;
1813 }
1814 
1815 /*------------------------------------------------------------------------------------------------- */
1817  struct TestSmData sSmData;
1818  struct TestSmData* smData = &sSmData;
1819  FwSmDesc_t smDesc;
1820 
1821  /* reset log */
1822  fwSm_logIndex = 0;
1823 
1824  /* Initialize data structure to hold the data of the embedding state machine */
1825  smData->counter_1 = 0;
1826  smData->counter_2 = 0;
1827  smData->flag_1 = 0;
1828  smData->flag_2 = 1;
1829  smData->logBase = 0;
1830 
1831  /* Create test SM */
1832  smDesc = FwSmMakeTestSM8(smData);
1833  if (smDesc==NULL)
1834  return smTestCaseFailure;
1835 
1836  /* Check configuration of state machine */
1837  if (FwSmCheckRec(smDesc) != smSuccess) {
1838  FwSmReleaseRec(smDesc);
1839  return smTestCaseFailure;
1840  }
1841 
1842  /* Start SM (this brings it to the FPS */
1843  fwSm_logIndex = 0; /* reset log */
1844  FwSmStart(smDesc);
1845  if ((smData->counter_2!=2) || (FwSmIsStarted(smDesc)!=0)) {
1846  FwSmReleaseRec(smDesc);
1847  return smTestCaseFailure;
1848  }
1849  if (fwSm_logIndex!=2) {
1850  FwSmReleaseRec(smDesc);
1851  return smTestCaseFailure;
1852  }
1853  FwSmReleaseRec(smDesc);
1854  return smTestCaseSuccess;
1855 }
1856 
1857 /*------------------------------------------------------------------------------------------------- */
1859  struct TestSmData sSmData;
1860  struct TestSmData* smData = &sSmData;
1861  FwSmDesc_t smDesc;
1862 
1863  /* reset log */
1864  fwSm_logIndex = 0;
1865 
1866  /* Initialize data structure to hold the data of the embedding state machine */
1867  smData->counter_1 = 0;
1868  smData->counter_2 = 0;
1869  smData->flag_1 = 0;
1870  smData->flag_2 = 1;
1871  smData->logBase = 0;
1872 
1873  /* Create test SM */
1874  smDesc = FwSmMakeTestSM9(smData);
1875  if (smDesc==NULL)
1876  return smTestCaseFailure;
1877 
1878  /* Check configuration of state machine */
1879  if (FwSmCheckRec(smDesc) != smSuccess) {
1880  FwSmReleaseRec(smDesc);
1881  return smTestCaseFailure;
1882  }
1883 
1884  /* Start SM (this brings it to S1 */
1885  fwSm_logIndex = 0; /* reset log */
1886  FwSmStart(smDesc);
1887  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
1888  FwSmReleaseRec(smDesc);
1889  return smTestCaseFailure;
1890  }
1891  if (fwSm_logIndex!=2) {
1892  FwSmReleaseRec(smDesc);
1893  return smTestCaseFailure;
1894  }
1895 
1896  /* Execute SM */
1897  FwSmExecute(smDesc);
1898  if ((smData->counter_1!=3) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
1899  FwSmReleaseRec(smDesc);
1900  return smTestCaseFailure;
1901  }
1902  if (fwSm_logIndex!=3) {
1903  FwSmReleaseRec(smDesc);
1904  return smTestCaseFailure;
1905  }
1906 
1907  /* Stop SM */
1908  FwSmStop(smDesc);
1909  if ((smData->counter_1!=7) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
1910  FwSmReleaseRec(smDesc);
1911  return smTestCaseFailure;
1912  }
1913  if (fwSm_logIndex!=4) {
1914  FwSmReleaseRec(smDesc);
1915  return smTestCaseFailure;
1916  }
1917 
1918  FwSmReleaseRec(smDesc);
1919  return smTestCaseSuccess;
1920 }
1921 
1922 /*------------------------------------------------------------------------------------------------- */
1924  struct TestSmData sSmData;
1925  struct TestSmData* smData = &sSmData;
1926  FwSmDesc_t smDesc;
1927 
1928  /* reset log */
1929  fwSm_logIndex = 0;
1930 
1931  /* Initialize data structure to hold the data of the embedding state machine */
1932  smData->counter_1 = 0;
1933  smData->counter_2 = 0;
1934  smData->flag_1 = 0;
1935  smData->flag_2 = 1;
1936  smData->logBase = 0;
1937 
1938  /* Create test SM */
1939  smDesc = FwSmMakeTestSM9Static(smData);
1940  if (smDesc==NULL)
1941  return smTestCaseFailure;
1942 
1943  /* Check configuration of state machine */
1944  if (FwSmCheckRec(smDesc) != smSuccess) {
1945  FwSmReleaseRec(smDesc);
1946  return smTestCaseFailure;
1947  }
1948 
1949  /* Start SM (this brings it to S1 */
1950  fwSm_logIndex = 0; /* reset log */
1951  FwSmStart(smDesc);
1952  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
1953  FwSmReleaseRec(smDesc);
1954  return smTestCaseFailure;
1955  }
1956  if (fwSm_logIndex!=2) {
1957  FwSmReleaseRec(smDesc);
1958  return smTestCaseFailure;
1959  }
1960 
1961  /* Execute SM */
1962  FwSmExecute(smDesc);
1963  if ((smData->counter_1!=3) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
1964  FwSmReleaseRec(smDesc);
1965  return smTestCaseFailure;
1966  }
1967  if (fwSm_logIndex!=3) {
1968  FwSmReleaseRec(smDesc);
1969  return smTestCaseFailure;
1970  }
1971 
1972  /* Stop SM */
1973  FwSmStop(smDesc);
1974  if ((smData->counter_1!=7) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
1975  FwSmReleaseRec(smDesc);
1976  return smTestCaseFailure;
1977  }
1978  if (fwSm_logIndex!=4) {
1979  FwSmReleaseRec(smDesc);
1980  return smTestCaseFailure;
1981  }
1982 
1983  return smTestCaseSuccess;
1984 }
1985 
1986 /*------------------------------------------------------------------------------------------------- */
1988  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
1989  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
1990  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
1991  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
1992  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
1993  FwSmDesc_t smDesc;
1994 
1995  /* Create a state machine with one state, one CPS, and four transitions */
1996  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
1997  FwSmSetData(smDesc, NULL);
1998 
1999  /* Attempt to add a CPS with zero out-going transitions */
2000  FwSmAddChoicePseudoState(smDesc, CPS1, 0);
2001  if (FwSmGetErrCode(smDesc) != smIllNOfOutTrans) {
2002  FwSmRelease(smDesc);
2003  return smTestCaseFailure;
2004  }
2005 
2006  /* Attempt to add a transition without first adding its source state */
2007  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
2008  if (FwSmGetErrCode(smDesc) != smUndefinedTransSrc) {
2009  FwSmRelease(smDesc);
2010  return smTestCaseFailure;
2011  }
2012 
2013  /* Attempt to add a transition without first adding its source state */
2014  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
2015  if (FwSmGetErrCode(smDesc) != smUndefinedTransSrc) {
2016  FwSmRelease(smDesc);
2017  return smTestCaseFailure;
2018  }
2019 
2020  FwSmRelease(smDesc);
2021  return smTestCaseSuccess;
2022 }
2023 
2024 /*------------------------------------------------------------------------------------------------- */
2026  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2027  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
2028  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
2029  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2030  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2031  FwSmDesc_t smDesc;
2032 
2033  /* Create a state machine with one state, one CPS, and four transitions */
2034  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2035  FwSmSetData(smDesc, NULL);
2036 
2037  /* Configure state machine - one transition has an illegal destination */
2038  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
2039  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
2040  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2041  FwSmAddTransStaToCps(smDesc, TR1, STATE_S1, 3, NULL, NULL); /* illegal destination */
2042  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
2043  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
2044 
2045  /* Check state machine and verify that an error is reported */
2046  if (FwSmCheck(smDesc) != smIllegalCDest) {
2047  FwSmRelease(smDesc);
2048  return smTestCaseFailure;
2049  }
2050  if (FwSmGetErrCode(smDesc) != smSuccess) {
2051  FwSmRelease(smDesc);
2052  return smTestCaseFailure;
2053  }
2054 
2055  FwSmRelease(smDesc);
2056  return smTestCaseSuccess;
2057 }
2058 
2059 /*------------------------------------------------------------------------------------------------- */
2061  struct TestSmData sSmData;
2062  struct TestSmData* smData = &sSmData;
2063  struct TestSmData sEsmData;
2064  struct TestSmData* esmData = &sEsmData;
2065  FwSmDesc_t smDesc;
2066 
2067  /* reset log */
2068  fwSm_logIndex = 0;
2069 
2070  /* Initialize data structure to hold the data of the embedding state machine */
2071  smData->counter_1 = 0;
2072  smData->counter_2 = 0;
2073  smData->flag_1 = 1;
2074  smData->flag_2 = 0;
2075  smData->logBase = 0;
2076 
2077  /* Initialize data structure to hold the data of the embedded state machine */
2078  esmData->counter_1 = 0;
2079  esmData->counter_2 = 0;
2080  esmData->flag_1 = 0;
2081  esmData->flag_2 = 0;
2082  esmData->logBase = 10;
2083 
2084  /* Create test SM */
2085  smDesc = FwSmMakeTestSM10(smData, esmData);
2086  if (smDesc==NULL)
2087  return smTestCaseFailure;
2088 
2089  /* Check configuration of state machine */
2090  if (FwSmCheckRec(smDesc) != smSuccess) {
2091  FwSmReleaseRec(smDesc);
2092  return smTestCaseFailure;
2093  }
2094 
2095  /* Start and execute SM (this brings the embedding SM in S1 - the execute command has no effect) */
2096  fwSm_logIndex = 0; /* reset log */
2097  FwSmStart(smDesc);
2098  FwSmExecute(smDesc);
2099  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2100  FwSmReleaseRec(smDesc);
2101  return smTestCaseFailure;
2102  }
2103  if ((esmData->counter_1!=0) || (esmData->counter_2!=0) || (FwSmGetCurState(FwSmGetEmbSm(smDesc, STATE_S2))!=0)) {
2104  FwSmReleaseRec(smDesc);
2105  return smTestCaseFailure;
2106  }
2107 
2108  /* Send TR1 command to SM (this brings the embedded SM to S2 and starts the embedded SM) */
2109  FwSmMakeTrans(smDesc, TR1);
2110  if ((smData->counter_1!=6) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
2111  FwSmReleaseRec(smDesc);
2112  return smTestCaseFailure;
2113  }
2114  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurStateEmb(smDesc)!=STATE_S1)) {
2115  FwSmReleaseRec(smDesc);
2116  return smTestCaseFailure;
2117  }
2118 
2119  /* Stop the embedded SM (this also stops the embedded SM) */
2120  FwSmStop(smDesc);
2121  if ((smData->counter_1!=10) || (smData->counter_2!=3) || (FwSmGetCurState(smDesc)!=0)) {
2122  FwSmReleaseRec(smDesc);
2123  return smTestCaseFailure;
2124  }
2125  if ((esmData->counter_1!=1) || (esmData->counter_2!=1) || (FwSmGetCurState(FwSmGetEmbSm(smDesc, STATE_S2))!=0)) {
2126  FwSmReleaseRec(smDesc);
2127  return smTestCaseFailure;
2128  }
2129 
2130  FwSmReleaseRec(smDesc);
2131  return smTestCaseSuccess;
2132 }
2133 
2134 /*------------------------------------------------------------------------------------------------- */
2136  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2137  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
2138  const FwSmCounterS1_t nOfTrans = 4; /* number of transitions */
2139  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2140  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2141  FwSmDesc_t smDesc;
2142 
2143  /* Create a state machine with one state, one CPS, and four transitions */
2144  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2145  FwSmSetData(smDesc, NULL);
2146 
2147  /* Configure state machine */
2148  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
2149  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
2150  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2151  FwSmAddTransStaToCps(smDesc, TR1, 2, CPS1, NULL, NULL);
2152  if (FwSmGetErrCode(smDesc) != smIllTransSrc) { /* illegal source */
2153  FwSmRelease(smDesc);
2154  return smTestCaseFailure;
2155  }
2156  FwSmAddTransStaToSta(smDesc, TR1, 2, STATE_S1, NULL, NULL);
2157  if (FwSmGetErrCode(smDesc) != smIllTransSrc) { /* illegal source */
2158  FwSmRelease(smDesc);
2159  return smTestCaseFailure;
2160  }
2161  FwSmAddTransCpsToFps(smDesc, 2, NULL, NULL);
2162  if (FwSmGetErrCode(smDesc) != smIllTransSrc) { /* illegal source */
2163  FwSmRelease(smDesc);
2164  return smTestCaseFailure;
2165  }
2166 
2167  /* Check state machine and verify that an error is reported */
2168  if (FwSmCheck(smDesc) == smSuccess) {
2169  FwSmRelease(smDesc);
2170  return smTestCaseFailure;
2171  }
2172 
2173  FwSmRelease(smDesc);
2174  return smTestCaseSuccess;
2175 }
2176 
2177 /*------------------------------------------------------------------------------------------------- */
2179  FwSmDesc_t smDesc;
2180 
2181  /* Create a state machine with an illegal number of states */
2182  smDesc = FwSmCreate(-1, 1, 1, 0, 0);
2183  if (smDesc != NULL)
2184  return smTestCaseFailure;
2185 
2186  /* Create a state machine with an illegal number of transitions */
2187  smDesc = FwSmCreate(1, 1, 0, 0, 0);
2188  if (smDesc != NULL)
2189  return smTestCaseFailure;
2190 
2191  /* Create a state machine with an illegal number of choice pseudo-states */
2192  smDesc = FwSmCreate(1, -1, 1, 0, 0);
2193  if (smDesc != NULL)
2194  return smTestCaseFailure;
2195 
2196  /* Create a state machine with an illegal number of actions */
2197  smDesc = FwSmCreate(1, 1, 1, -1, 0);
2198  if (smDesc != NULL)
2199  return smTestCaseFailure;
2200 
2201  /* Create a state machine with an illegal number of guards */
2202  smDesc = FwSmCreate(1, 1, 1, 0, -1);
2203  if (smDesc != NULL)
2204  return smTestCaseFailure;
2205 
2206  return smTestCaseSuccess;
2207 }
2208 
2209 /*------------------------------------------------------------------------------------------------- */
2211  struct TestSmData sSmData;
2212  struct TestSmData* smData = &sSmData;
2213  FwSmDesc_t smDesc;
2214 
2215  /* reset log */
2216  fwSm_logIndex = 0;
2217 
2218  /* Initialize data structure to hold the data of the embedding state machine */
2219  smData->counter_1 = 0;
2220  smData->counter_2 = 0;
2221  smData->flag_1 = 0;
2222  smData->flag_2 = 0;
2223  smData->logBase = 0;
2224 
2225  /* Create test SM */
2226  smDesc = FwSmMakeTestSM2(smData);
2227  if (smDesc==NULL)
2228  return smTestCaseFailure;
2229 
2230  /* Check configuration of state machine */
2231  if (FwSmCheck(smDesc) != smSuccess) {
2232  FwSmRelease(smDesc);
2233  return smTestCaseFailure;
2234  }
2235 
2236  /* Start SM (this leaves it in an undefined state because both flag_1 and flag_2 are false */
2237  fwSm_logIndex = 0; /* reset log */
2238  FwSmStart(smDesc);
2239  if ((smData->counter_1!=0) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
2240  FwSmRelease(smDesc);
2241  return smTestCaseFailure;
2242  }
2243  if ((fwSm_logIndex!=1) || (FwSmGetErrCode(smDesc)!=smTransErr)) {
2244  FwSmRelease(smDesc);
2245  return smTestCaseFailure;
2246  }
2247 
2248  FwSmRelease(smDesc);
2249  return smTestCaseSuccess;
2250 }
2251 
2252 /*------------------------------------------------------------------------------------------------- */
2254  struct TestSmData sSmData;
2255  struct TestSmData* smData = &sSmData;
2256  FwSmDesc_t smDesc;
2257 
2258  /* reset log */
2259  fwSm_logIndex = 0;
2260 
2261  /* Initialize data structure to hold the data of the embedding state machine */
2262  smData->counter_1 = 0;
2263  smData->counter_2 = 0;
2264  smData->flag_1 = 0;
2265  smData->flag_2 = 0;
2266  smData->logBase = 0;
2267 
2268  /* Create test SM */
2269  smDesc = FwSmMakeTestSM11(smData);
2270  if (smDesc==NULL)
2271  return smTestCaseFailure;
2272 
2273  /* Check configuration of state machine */
2274  if (FwSmCheck(smDesc) != smSuccess) {
2275  FwSmRelease(smDesc);
2276  return smTestCaseFailure;
2277  }
2278 
2279  /* Start SM (this causes it to terminate immediately) */
2280  fwSm_logIndex = 0; /* reset log */
2281  FwSmStart(smDesc);
2282  if ((smData->counter_1!=0) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
2283  return smTestCaseFailure;
2284  }
2285 
2286  return smTestCaseSuccess;
2287 }
2288 
2289 /*------------------------------------------------------------------------------------------------- */
2291  struct TestSmData sSmData;
2292  struct TestSmData* smData = &sSmData;
2293  FwSmDesc_t smDesc;
2294 
2295  /* reset log */
2296  fwSm_logIndex = 0;
2297 
2298  /* Initialize data structure to hold the data of the embedding state machine */
2299  smData->counter_1 = 0;
2300  smData->counter_2 = 0;
2301  smData->flag_1 = 1;
2302  smData->flag_2 = 0;
2303  smData->logBase = 0;
2304 
2305  /* Create test SM */
2306  smDesc = FwSmMakeTestSM12(smData);
2307  if (smDesc==NULL)
2308  return smTestCaseFailure;
2309 
2310  /* Check configuration of state machine (state S1 is unreachable) */
2311  if (FwSmCheck(smDesc) != smUnreachablePState) {
2312  FwSmRelease(smDesc);
2313  return smTestCaseFailure;
2314  }
2315 
2316  /* Start SM and verifies that transition encounters an error */
2317  fwSm_logIndex = 0; /* reset log */
2318  FwSmStart(smDesc);
2319  if (FwSmGetErrCode(smDesc) != smTransErr) {
2320  FwSmRelease(smDesc);
2321  return smTestCaseFailure;
2322  }
2323 
2324  FwSmRelease(smDesc);
2325  return smTestCaseSuccess;
2326 }
2327 
2328 /*------------------------------------------------------------------------------------------------- */
2330  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2331  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
2332  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
2333  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2334  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2335  FwSmDesc_t smDesc;
2336 
2337  /* Create a state machine with one state, one choice pseudo-state and three transitions */
2338  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2339  FwSmSetData(smDesc, NULL);
2340 
2341  /* Configure state with too many out-going transitions */
2342  FwSmAddState(smDesc, STATE_S1, 3, NULL, NULL, NULL, NULL);
2343  if (FwSmGetErrCode(smDesc) != smTooManyOutTrans) {
2344  FwSmRelease(smDesc);
2345  return smTestCaseFailure;
2346  }
2347 
2348  /* Configure choice pseudo-state with too many out-going transitions */
2349  FwSmAddChoicePseudoState(smDesc, CPS1, 3);
2350  if (FwSmGetErrCode(smDesc) != smTooManyOutTrans) {
2351  FwSmRelease(smDesc);
2352  return smTestCaseFailure;
2353  }
2354 
2355  FwSmRelease(smDesc);
2356  return smTestCaseSuccess;
2357 }
2358 
2359 /*------------------------------------------------------------------------------------------------- */
2361  const FwSmCounterS1_t nOfPStates = 3; /* number of proper states */
2362  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
2363  const FwSmCounterS1_t nOfTrans = 1; /* number of transitions */
2364  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2365  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2366  FwSmDesc_t smDesc;
2367 
2368  /* Create a state machine with three state and one transition */
2369  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2370  FwSmSetData(smDesc, NULL);
2371 
2372  /* Configure state with an entry action (not allowed because no actions have been declared */
2373  FwSmAddState(smDesc, STATE_S1, 0, &SmDummyAction, NULL, NULL, NULL);
2374  if (FwSmGetErrCode(smDesc) != smTooManyActions) {
2375  FwSmRelease(smDesc);
2376  return smTestCaseFailure;
2377  }
2378 
2379  /* Configure state with an exit action (not allowed because no actions have been declared */
2380  FwSmAddState(smDesc, STATE_S2, 0, NULL, &SmDummyAction, NULL, NULL);
2381  if (FwSmGetErrCode(smDesc) != smTooManyActions) {
2382  FwSmRelease(smDesc);
2383  return smTestCaseFailure;
2384  }
2385 
2386  /* Configure state with a do-action (not allowed because no actions have been declared */
2387  FwSmAddState(smDesc, STATE_S3, 0, NULL, NULL, &SmDummyAction, NULL);
2388  if (FwSmGetErrCode(smDesc) != smTooManyActions) {
2389  FwSmRelease(smDesc);
2390  return smTestCaseFailure;
2391  }
2392 
2393  FwSmRelease(smDesc);
2394  return smTestCaseSuccess;
2395 }
2396 
2397 /*------------------------------------------------------------------------------------------------- */
2399  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2400  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
2401  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
2402  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2403  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2404  FwSmDesc_t smDesc;
2405 
2406  /* Create a state machine with one state and three transitions */
2407  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2408  FwSmSetData(smDesc, NULL);
2409 
2410  /* Configure state */
2411  FwSmAddState(smDesc, STATE_S1, 2, NULL, NULL, NULL, NULL);
2412  if (FwSmGetErrCode(smDesc) != smSuccess) {
2413  FwSmRelease(smDesc);
2414  return smTestCaseFailure;
2415  }
2416 
2417  /* Configure transition with an action (not allowed because no actions have been declared */
2418  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, &SmDummyAction, NULL);
2419  if (FwSmGetErrCode(smDesc) != smTooManyActions) {
2420  FwSmRelease(smDesc);
2421  return smTestCaseFailure;
2422  }
2423 
2424  /* Configure transition with a guard (not allowed because no guards have been declared */
2425  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, &SmDummyGuard);
2426  if (FwSmGetErrCode(smDesc) != smTooManyGuards) {
2427  FwSmRelease(smDesc);
2428  return smTestCaseFailure;
2429  }
2430 
2431  FwSmRelease(smDesc);
2432  return smTestCaseSuccess;
2433 }
2434 
2435 /*------------------------------------------------------------------------------------------------- */
2437  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2438  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
2439  const FwSmCounterS1_t nOfTrans = 2; /* number of transitions */
2440  const FwSmCounterS1_t nOfActions = 1; /* number of actions */
2441  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2442  FwSmDesc_t smDesc;
2443 
2444  /* Create a state machine with one state, two transitions, and one action */
2445  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2446  FwSmSetData(smDesc, NULL);
2447 
2448  /* Configure state */
2449  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
2450  if (FwSmGetErrCode(smDesc) != smSuccess) {
2451  FwSmRelease(smDesc);
2452  return smTestCaseFailure;
2453  }
2454 
2455  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2456  if (FwSmGetErrCode(smDesc) != smSuccess) {
2457  FwSmRelease(smDesc);
2458  return smTestCaseFailure;
2459  }
2460 
2461  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
2462  if (FwSmGetErrCode(smDesc) != smSuccess) {
2463  FwSmRelease(smDesc);
2464  return smTestCaseFailure;
2465  }
2466 
2467  if (FwSmCheck(smDesc) != smTooFewActions) {
2468  FwSmRelease(smDesc);
2469  return smTestCaseFailure;
2470  }
2471 
2472  FwSmRelease(smDesc);
2473  return smTestCaseSuccess;
2474 }
2475 
2476 /*------------------------------------------------------------------------------------------------- */
2478  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2479  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
2480  const FwSmCounterS1_t nOfTrans = 2; /* number of transitions */
2481  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2482  const FwSmCounterS1_t nOfGuards = 1; /* number of guards */
2483  FwSmDesc_t smDesc;
2484 
2485  /* Create a state machine with one state, two transitions, and one guard */
2486  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2487  FwSmSetData(smDesc, NULL);
2488 
2489  /* Configure state */
2490  FwSmAddState(smDesc, STATE_S1, 1, NULL, NULL, NULL, NULL);
2491  if (FwSmGetErrCode(smDesc) != smSuccess) {
2492  FwSmRelease(smDesc);
2493  return smTestCaseFailure;
2494  }
2495 
2496  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2497  if (FwSmGetErrCode(smDesc) != smSuccess) {
2498  FwSmRelease(smDesc);
2499  return smTestCaseFailure;
2500  }
2501 
2502  FwSmAddTransStaToFps(smDesc, TR1, STATE_S1, NULL, NULL);
2503  if (FwSmGetErrCode(smDesc) != smSuccess) {
2504  FwSmRelease(smDesc);
2505  return smTestCaseFailure;
2506  }
2507 
2508  if (FwSmCheck(smDesc) != smTooFewGuards) {
2509  FwSmRelease(smDesc);
2510  return smTestCaseFailure;
2511  }
2512 
2513  FwSmRelease(smDesc);
2514  return smTestCaseSuccess;
2515 }
2516 
2517 /*------------------------------------------------------------------------------------------------- */
2519  const FwSmCounterS1_t nOfPStates = 2; /* number of proper states */
2520  const FwSmCounterS1_t nOfCStates = 0; /* number of choice pseudo-states */
2521  const FwSmCounterS1_t nOfTrans = 1; /* number of transitions */
2522  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2523  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2524  FwSmDesc_t smDesc;
2525 
2526  /* Create and configure the test state machine */
2527  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2528  FwSmSetData(smDesc, NULL);
2529 
2530  FwSmAddState(smDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
2531  FwSmAddState(smDesc, STATE_S2, 0, NULL, NULL, NULL, NULL);
2532 
2533  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2534 
2535  /* Check that configuration error is detected */
2536  if (FwSmCheck(smDesc) != smUnreachablePState) {
2537  FwSmRelease(smDesc);
2538  return smTestCaseFailure;
2539  }
2540 
2541  FwSmRelease(smDesc);
2542  return smTestCaseSuccess;
2543 }
2544 
2545 /*------------------------------------------------------------------------------------------------- */
2547  const FwSmCounterS1_t nOfPStates = 1; /* number of proper states */
2548  const FwSmCounterS1_t nOfCStates = 1; /* number of choice pseudo-states */
2549  const FwSmCounterS1_t nOfTrans = 3; /* number of transitions */
2550  const FwSmCounterS1_t nOfActions = 0; /* number of actions */
2551  const FwSmCounterS1_t nOfGuards = 0; /* number of guards */
2552  FwSmDesc_t smDesc;
2553 
2554  /* Create and configure the test state machine */
2555  smDesc = FwSmCreate(nOfPStates, nOfCStates, nOfTrans, nOfActions, nOfGuards);
2556  FwSmSetData(smDesc, NULL);
2557 
2558  FwSmAddState(smDesc, STATE_S1, 0, NULL, NULL, NULL, NULL);
2559  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
2560 
2561  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2562  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
2563  FwSmAddTransCpsToSta(smDesc, CPS1, STATE_S1, NULL, NULL);
2564 
2565  /* Check that configuration error is detected */
2566  if (FwSmCheck(smDesc) != smUnreachableCState) {
2567  FwSmRelease(smDesc);
2568  return smTestCaseFailure;
2569  }
2570 
2571  FwSmRelease(smDesc);
2572  return smTestCaseSuccess;
2573 }
2574 
2575 /*------------------------------------------------------------------------------------------------- */
2577  struct TestSmData sSmData;
2578  struct TestSmData* smData = &sSmData;
2579  FwSmDesc_t smDesc;
2580 
2581  /* reset log */
2582  fwSm_logIndex = 0;
2583 
2584  /* Initialize data structure holding the state machine data */
2585  smData->counter_1 = 0;
2586  smData->counter_2 = 0;
2587  smData->flag_1 = 1;
2588  smData->flag_2 = 0;
2589  smData->logBase = 0;
2590 
2591  /* Create test SM */
2592  smDesc = FwSmMakeTestSM1Static(smData);
2593  if (smDesc==NULL)
2594  return smTestCaseFailure;
2595 
2596  /* Check configuration of state machine */
2597  if (FwSmCheck(smDesc) != smSuccess) {
2598  return smTestCaseFailure;
2599  }
2600 
2601  /* Attempt executing a stopped state machine and check that nothing happens */
2602  FwSmExecute(smDesc);
2603  if ((smData->counter_1!=0) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=0) ||
2604  (smData->logBase!=0)) {
2605  return smTestCaseFailure;
2606  }
2607 
2608  /* Start SM (this brings it to state S1) */
2609  FwSmStart(smDesc);
2610  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2611  return smTestCaseFailure;
2612  }
2613 
2614  /* Execute state machine twice and check success */
2615  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
2616  if ((smData->counter_1!=3) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2617  return smTestCaseFailure;
2618  }
2619 
2620  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
2621  if ((smData->counter_1!=5) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2622  return smTestCaseFailure;
2623  }
2624 
2625  /* Stop state machine twice and check success */
2626  FwSmStop(smDesc);
2627  if ((smData->counter_1!=5) || (smData->counter_2!=1) || (FwSmGetCurState(smDesc)!=0)) {
2628  return smTestCaseFailure;
2629  }
2630 
2631  return smTestCaseSuccess;
2632 }
2633 
2634 /*------------------------------------------------------------------------------------------------- */
2636  struct TestSmData sSmData;
2637  struct TestSmData* smData = &sSmData;
2638  struct TestSmData sEsmData;
2639  struct TestSmData* esmData = &sEsmData;
2640  FILE* outfile;
2641  FwSmDesc_t smDesc;
2642 
2643  outfile = fopen("FwSmPrint.out","w");
2644 
2645  fprintf(outfile,"\n===== TEST STATE MACHINE SM1 =====\n");
2646  smDesc = FwSmMakeTestSM1(smData);
2647  FwSmPrintConfig(smDesc, outfile);
2648  FwSmRelease(smDesc);
2649 
2650  fprintf(outfile,"\n===== TEST STATE MACHINE SM1 (Static Initialization) =====\n");
2651  smDesc = FwSmMakeTestSM1Static(smData);
2652  FwSmPrintConfig(smDesc, outfile);
2653 
2654  fprintf(outfile,"\n===== TEST STATE MACHINE SM2 =====\n");
2655  smDesc = FwSmMakeTestSM2(smData);
2656  FwSmPrintConfig(smDesc, outfile);
2657  FwSmRelease(smDesc);
2658 
2659  fprintf(outfile,"\n===== TEST STATE MACHINE SM3 =====\n");
2660  smDesc = FwSmMakeTestSM3(smData, esmData);
2661  FwSmPrintConfig(smDesc, outfile);
2662  FwSmReleaseRec(smDesc);
2663 
2664  fprintf(outfile,"\n===== TEST STATE MACHINE SM4 =====\n");
2665  smDesc = FwSmMakeTestSM4(smData);
2666  FwSmPrintConfig(smDesc, outfile);
2667  FwSmRelease(smDesc);
2668 
2669  fprintf(outfile,"\n===== TEST STATE MACHINE SM5 =====\n");
2670  smDesc = FwSmMakeTestSM5(smData);
2671  FwSmPrintConfig(smDesc, outfile);
2672  FwSmRelease(smDesc);
2673 
2674  fprintf(outfile,"\n===== TEST STATE MACHINE SM5 (Static Initialization) =====\n");
2675  smDesc = FwSmMakeTestSM5Static(smData);
2676  FwSmPrintConfig(smDesc, outfile);
2677 
2678  fprintf(outfile,"\n===== TEST STATE MACHINE SM5 (Direct Initialization) =====\n");
2679  smDesc = FwSmMakeTestSM5Dir(smData);
2680  FwSmPrintConfig(smDesc, outfile);
2681 
2682  fprintf(outfile,"\n===== TEST STATE MACHINE SM6 =====\n");
2683  smDesc = FwSmMakeTestSM6(smData, esmData);
2684  FwSmPrintConfig(smDesc, outfile);
2685  FwSmReleaseRec(smDesc);
2686 
2687  fprintf(outfile,"\n===== TEST STATE MACHINE SM7 =====\n");
2688  smDesc = FwSmMakeTestSM7(smData);
2689  FwSmPrintConfig(smDesc, outfile);
2690  FwSmRelease(smDesc);
2691 
2692  fprintf(outfile,"\n===== TEST STATE MACHINE SM8 =====\n");
2693  smDesc = FwSmMakeTestSM8(smData);
2694  FwSmPrintConfig(smDesc, outfile);
2695  FwSmRelease(smDesc);
2696 
2697  fprintf(outfile,"\n===== TEST STATE MACHINE SM9 =====\n");
2698  smDesc = FwSmMakeTestSM9(smData);
2699  FwSmPrintConfig(smDesc, outfile);
2700  FwSmRelease(smDesc);
2701 
2702  fprintf(outfile,"\n===== TEST STATE MACHINE SM9 (Static Initialization) =====\n");
2703  smDesc = FwSmMakeTestSM9Static(smData);
2704  FwSmPrintConfig(smDesc, outfile);
2705 
2706  fprintf(outfile,"\n===== TEST STATE MACHINE SM10 =====\n");
2707  smDesc = FwSmMakeTestSM10(smData, esmData);
2708  FwSmPrintConfig(smDesc, outfile);
2709 
2710  fprintf(outfile,"\n===== TEST STATE MACHINE SM10 (After it has been started) =====\n");
2711  FwSmStart(smDesc);
2712  FwSmPrintConfig(smDesc, outfile);
2713  FwSmReleaseRec(smDesc);
2714 
2715  fprintf(outfile,"\n===== TEST STATE MACHINE SM11 (Static Initialization) =====\n");
2716  smDesc = FwSmMakeTestSM11(smData);
2717  FwSmPrintConfig(smDesc, outfile);
2718 
2719  fprintf(outfile,"\n===== TEST STATE MACHINE SM13 =====\n");
2720  smDesc = FwSmMakeTestSM13(smData);
2721  FwSmPrintConfig(smDesc, outfile);
2722  FwSmRelease(smDesc);
2723 
2724  fclose(outfile);
2725 
2726  return smTestCaseSuccess;
2727 }
2728 
2729 /*------------------------------------------------------------------------------------------------- */
2731  FILE* outfile;
2732  FwSmDesc_t smDesc;
2733 
2734  outfile = fopen("FwSmPrint.out","a");
2735 
2736  fprintf(outfile,"\n===== FwSmPrint is called with a NULL State Machine Descriptor =====\n");
2737  FwSmPrintConfig(NULL, outfile);
2738 
2739  fprintf(outfile,"\n===== TEST STATE MACHINE SM12 (this SM has an illegal configuration) =====\n");
2740  smDesc = FwSmMakeTestSM12(NULL);
2741  FwSmPrintConfig(smDesc, outfile);
2742  FwSmRelease(smDesc);
2743 
2744  fprintf(outfile,"\n===== FwSmPrint is called with an unconfigured State Machine Descriptor =====\n");
2745  smDesc = FwSmCreate(2, 1, 3, 3, 3);
2746  FwSmPrintConfig(smDesc, outfile);
2747  FwSmRelease(smDesc);
2748 
2749  fprintf(outfile,"\n===== FwSmPrint is called on a State Machine Descriptor with Undefined State =====\n");
2750  smDesc = FwSmCreate(1, 0, 2, 0, 0);
2751  FwSmAddTransIpsToSta(smDesc, STATE_S1, NULL);
2752  FwSmPrintConfig(smDesc, outfile);
2753  FwSmRelease(smDesc);
2754 
2755  fprintf(outfile,"\n===== FwSmPrint is called on a State Machine Descriptor with Undefined Choice Pseudo-State =====\n");
2756  smDesc = FwSmCreate(0, 1, 3, 0, 0);
2757  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
2758  FwSmPrintConfig(smDesc, outfile);
2759  FwSmRelease(smDesc);
2760 
2761  fprintf(outfile,"\n===== FwSmPrint is called on a State Machine Descriptor with no states =====\n");
2762  smDesc = FwSmCreate(0, 1, 3, 0, 0);
2763  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
2764  FwSmAddTransIpsToCps(smDesc, CPS1, NULL);
2765  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
2766  FwSmAddTransCpsToFps(smDesc, CPS1, NULL, NULL);
2767  FwSmPrintConfig(smDesc, outfile);
2768  FwSmRelease(smDesc);
2769 
2770  fclose(outfile);
2771 
2772  return smTestCaseSuccess;
2773 }
2774 
2775 /*------------------------------------------------------------------------------------------------- */
2777  struct TestSmData sSmData;
2778  struct TestSmData* smData = &sSmData;
2779  FwSmDesc_t smDesc;
2780 
2781  /* reset log */
2782  fwSm_logIndex = 0;
2783 
2784  /* Initialize data structure holding the state machine data */
2785  smData->counter_1 = 0;
2786  smData->counter_2 = 0;
2787  smData->flag_1 = 1;
2788  smData->flag_2 = 0;
2789  smData->logBase = 0;
2790 
2791  /* Create test SM */
2792  smDesc = FwSmMakeTestSM13(smData);
2793  if (smDesc==NULL)
2794  return smTestCaseFailure;
2795 
2796  /* Check configuration of state machine */
2797  if (FwSmCheck(smDesc) != smSuccess) {
2798  FwSmRelease(smDesc);
2799  return smTestCaseFailure;
2800  }
2801 
2802  /* Start SM (this brings it to state S1) */
2803  FwSmStart(smDesc);
2804  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2805  FwSmRelease(smDesc);
2806  return smTestCaseFailure;
2807  }
2808 
2809  /* Execute state machine and check success */
2810  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
2811  if ((smData->counter_1!=8) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
2812  FwSmRelease(smDesc);
2813  return smTestCaseFailure;
2814  }
2815 
2816  smData->flag_1 = 0;
2817  smData->flag_2 = 1;
2818 
2819  FwSmMakeTrans(smDesc, FW_TR_EXECUTE);
2820  if ((smData->counter_1!=14) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=0)) {
2821  FwSmRelease(smDesc);
2822  return smTestCaseFailure;
2823  }
2824 
2825  FwSmRelease(smDesc);
2826  return smTestCaseSuccess;
2827 }
2828 
2829 /*------------------------------------------------------------------------------------------------- */
2831  struct TestSmData sSmData;
2832  struct TestSmData* smData = &sSmData;
2833  FwSmDesc_t smDescBase, smDescDer;
2834 
2835  /* reset log */
2836  fwSm_logIndex = 0;
2837 
2838  /* Initialize data structures for the base state machine SM5 */
2839  smData->counter_1 = 0;
2840  smData->counter_2 = 0;
2841  smData->flag_1 = 1;
2842  smData->flag_2 = 0;
2843  smData->logBase = 0;
2844 
2845  /* Create the base state machine */
2846  smDescBase = FwSmMakeTestSM5(NULL);
2847  if (smDescBase==NULL)
2848  return smTestCaseFailure;
2849 
2850  /* Check configuration of base state machine */
2851  if (FwSmCheckRec(smDescBase) != smSuccess) {
2852  FwSmReleaseRec(smDescBase);
2853  return smTestCaseFailure;
2854  }
2855 
2856  /* Create the derived state machine */
2857  smDescDer = FwSmCreateDer(smDescBase);
2858 
2859  /* Set the data structure for the derived state machine */
2860  FwSmSetData(smDescDer, smData);
2861 
2862  /* Check configuration of derived state machine */
2863  if (FwSmCheckRec(smDescDer) != smSuccess) {
2864  FwSmRelease(smDescBase);
2865  FwSmReleaseDer(smDescDer);
2866  return smTestCaseFailure;
2867  }
2868 
2869  /* Start SM (this brings it to state S1) */
2870  FwSmStart(smDescDer);
2871  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
2872  FwSmRelease(smDescBase);
2873  FwSmReleaseDer(smDescDer);
2874  return smTestCaseFailure;
2875  }
2876 
2877  /* Send transition command TR4 to SM and check that this has no effect */
2878  fwSm_logIndex = 0;
2879  FwSmMakeTrans(smDescDer, TR4);
2880  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1) || (fwSm_logIndex!=0)) {
2881  FwSmRelease(smDescBase);
2882  FwSmReleaseDer(smDescDer);
2883  return smTestCaseFailure;
2884  }
2885 
2886  /* Set guard to prevent transition TR2 from S1 to S2 and then check that transition does not take place */
2887  smData->flag_1 = 0;
2888  FwSmMakeTrans(smDescDer, TR2);
2889  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1) || (fwSm_logIndex!=0)) {
2890  FwSmRelease(smDescBase);
2891  FwSmReleaseDer(smDescDer);
2892  return smTestCaseFailure;
2893  }
2894 
2895  /* Set guard to allow transition TR2 from S1 to S2 and then check that transition does take place */
2896  smData->flag_1 = 1;
2897  FwSmMakeTrans(smDescDer, TR2);
2898  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDescDer)!=STATE_S2) || (fwSm_logIndex!=3)) {
2899  FwSmRelease(smDescBase);
2900  FwSmReleaseDer(smDescDer);
2901  return smTestCaseFailure;
2902  }
2903  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
2904  FwSmRelease(smDescBase);
2905  FwSmReleaseDer(smDescDer);
2906  return smTestCaseFailure;
2907  }
2908 
2909  FwSmRelease(smDescBase);
2910  FwSmReleaseDer(smDescDer);
2911  return smTestCaseSuccess;
2912 }
2913 
2914 /*------------------------------------------------------------------------------------------------- */
2916  struct TestSmData sSmData;
2917  struct TestSmData* smData = &sSmData;
2918  FwSmDesc_t smDescBase, smDescDer;
2919 
2920  /* reset log */
2921  fwSm_logIndex = 0;
2922 
2923  /* Initialize data structures for the base state machine SM1 */
2924  smData->counter_1 = 0;
2925  smData->counter_2 = 0;
2926  smData->flag_1 = 0;
2927  smData->flag_2 = 0;
2928  smData->logBase = 0;
2929 
2930  /* Create the base state machine */
2931  smDescBase = FwSmMakeTestSM1(smData);
2932  if (smDescBase==NULL)
2933  return smTestCaseFailure;
2934 
2935  /* Check configuration of base state machine */
2936  if (FwSmCheckRec(smDescBase) != smSuccess) {
2937  FwSmReleaseRec(smDescBase);
2938  return smTestCaseFailure;
2939  }
2940 
2941  /* Create the derived state machine */
2942  smDescDer = FwSmMakeTestSMDer1(smDescBase, smData);
2943 
2944  /* Check configuration of derived state machine */
2945  if (FwSmCheck(smDescDer) != smSuccess) {
2946  FwSmReleaseDer(smDescDer);
2947  FwSmRelease(smDescBase);
2948  return smTestCaseFailure;
2949  }
2950 
2951  /* Start SM (this brings it to state S1) */
2952  FwSmStart(smDescDer);
2953  if ((smData->counter_1!=8) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
2954  FwSmReleaseDer(smDescDer);
2955  FwSmRelease(smDescBase);
2956  return smTestCaseFailure;
2957  }
2958 
2959  /* Execute state machine twice and check success */
2960  FwSmMakeTrans(smDescDer, FW_TR_EXECUTE);
2961  if ((smData->counter_1!=10) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
2962  FwSmReleaseDer(smDescDer);
2963  FwSmRelease(smDescBase);
2964  return smTestCaseFailure;
2965  }
2966 
2967  FwSmMakeTrans(smDescDer, FW_TR_EXECUTE);
2968  if ((smData->counter_1!=12) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
2969  FwSmReleaseDer(smDescDer);
2970  FwSmRelease(smDescBase);
2971  return smTestCaseFailure;
2972  }
2973 
2974  /* Command transition from S1 to FPS and check that nothing happens (guard is not true) */
2975  FwSmMakeTrans(smDescDer, TR_S1_FPS);
2976  if ((smData->counter_1!=12) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
2977  FwSmReleaseDer(smDescDer);
2978  FwSmRelease(smDescBase);
2979  return smTestCaseFailure;
2980  }
2981 
2982  /* Command transition from S1 to FPS and check that transition is executed (guard is true) */
2983  smData->flag_2 = 1;
2984  FwSmMakeTrans(smDescDer, TR_S1_FPS);
2985  if ((smData->counter_1!=12) || (smData->counter_2!=2) || (FwSmGetCurState(smDescDer)!=0)) {
2986  FwSmReleaseDer(smDescDer);
2987  FwSmRelease(smDescBase);
2988  return smTestCaseFailure;
2989  }
2990 
2991  FwSmReleaseDer(smDescDer);
2992  FwSmRelease(smDescBase);
2993  return smTestCaseSuccess;
2994 }
2995 
2996 /*------------------------------------------------------------------------------------------------- */
2998  struct TestSmData sSmDataBase;
2999  struct TestSmData* smDataBase = &sSmDataBase;
3000  struct TestSmData sEsmDataBase;
3001  struct TestSmData* esmDataBase = &sEsmDataBase;
3002  struct TestSmData sSmDataDer;
3003  struct TestSmData* smDataDer = &sSmDataDer;
3004  struct TestSmData sEsmDataDer;
3005  struct TestSmData* esmDataDer = &sEsmDataDer;
3006  FwSmDesc_t smDescBase, smDescDer, esmDescDer;
3007 
3008  /* reset log */
3009  fwSm_logIndex = 0;
3010 
3011  /* Create the base state machine */
3012  smDescBase = FwSmMakeTestSM6(smDataBase, esmDataBase);
3013  if (smDescBase==NULL)
3014  return smTestCaseFailure;
3015 
3016  /* Check configuration of base state machine */
3017  if (FwSmCheckRec(smDescBase) != smSuccess) {
3018  FwSmReleaseRec(smDescBase);
3019  return smTestCaseFailure;
3020  }
3021 
3022  /* Start the base state machine */
3023  FwSmStart(smDescBase);
3024 
3025  /* Create the derived state machine */
3026  smDescDer = FwSmCreateDer(smDescBase);
3027 
3028  /* Initialize and set the data structure for the derived state machine (Outer SM) */
3029  smDataDer->counter_1 = 0;
3030  smDataDer->counter_2 = 0;
3031  smDataDer->flag_1 = 1;
3032  smDataDer->flag_2 = 0;
3033  smDataDer->logBase = 0;
3034  FwSmSetData(smDescDer, smDataDer);
3035 
3036  /* Get the SM embedded in state S2 of the derived SM */
3037  esmDescDer = FwSmGetEmbSm(smDescDer,2);
3038 
3039  /* Initialize and set the data structure for the derived state machine (Embedded SM) */
3040  esmDataDer->counter_1 = 0;
3041  esmDataDer->counter_2 = 0;
3042  esmDataDer->flag_1 = 1;
3043  esmDataDer->flag_2 = 0;
3044  esmDataDer->logBase = 10;
3045  FwSmSetData(esmDescDer, esmDataDer);
3046 
3047  /* Check configuration of derived state machine */
3048  if (FwSmCheckRec(smDescDer) != smSuccess) {
3049  FwSmReleaseDer(smDescDer);
3050  FwSmReleaseDer(esmDescDer);
3051  FwSmReleaseRec(smDescBase);
3052  return smTestCaseFailure;
3053  }
3054 
3055  /* Start and execute SM (this brings the embedding SM in S2 and starts the ESM) */
3056  fwSm_logIndex = 0; /* reset log */
3057  FwSmStart(smDescDer);
3058  FwSmExecute(smDescDer);
3059  if ((smDataDer->counter_1!=8) || (smDataDer->counter_2!=2) || (FwSmGetCurState(smDescDer)!=STATE_S2)) {
3060  FwSmReleaseDer(smDescDer);
3061  FwSmReleaseDer(esmDescDer);
3062  FwSmReleaseRec(smDescBase);
3063  return smTestCaseFailure;
3064  }
3065  if ((esmDataDer->counter_1!=1) || (esmDataDer->counter_2!=1) || (FwSmGetCurStateEmb(smDescDer)!=STATE_S1)) {
3066  FwSmReleaseDer(smDescDer);
3067  FwSmReleaseDer(esmDescDer);
3068  FwSmReleaseRec(smDescBase);
3069  return smTestCaseFailure;
3070  }
3071 
3072  /* Send TR2 command to SM (this has no effect on the SM but causes the ESM to go from S1 to S2) */
3073  FwSmMakeTrans(smDescDer, TR2);
3074  if ((smDataDer->counter_1!=8) || (smDataDer->counter_2!=2) || (FwSmGetCurState(smDescDer)!=STATE_S2)) {
3075  FwSmReleaseDer(smDescDer);
3076  FwSmReleaseDer(esmDescDer);
3077  FwSmReleaseRec(smDescBase);
3078  return smTestCaseFailure;
3079  }
3080  if ((esmDataDer->counter_1!=6) || (esmDataDer->counter_2!=2) || (FwSmGetCurStateEmb(smDescDer)!=STATE_S2)) {
3081  FwSmReleaseDer(smDescDer);
3082  FwSmReleaseDer(esmDescDer);
3083  FwSmReleaseRec(smDescBase);
3084  return smTestCaseFailure;
3085  }
3086  fwSm_logIndex = 0;
3087 
3088  /* Execute the SM (this causes the do-action of the S2 of both the SM and ESM to be executed and then triggers */
3089  /* a transition from S2 to S1 in the SM) */
3090  FwSmExecute(smDescDer);
3091  if ((smDataDer->counter_1!=15) || (smDataDer->counter_2!=3) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3092  FwSmReleaseDer(smDescDer);
3093  FwSmReleaseDer(esmDescDer);
3094  FwSmReleaseRec(smDescBase);
3095  return smTestCaseFailure;
3096  }
3097  if ((esmDataDer->counter_1!=12) || (esmDataDer->counter_2!=2) || (FwSmGetCurState(FwSmGetEmbSm(smDescDer, STATE_S2))!=0)) {
3098  FwSmReleaseDer(smDescDer);
3099  FwSmReleaseDer(esmDescDer);
3100  FwSmReleaseRec(smDescBase);
3101  return smTestCaseFailure;
3102  }
3103  if (fwSm_logIndex!=6) {
3104  FwSmReleaseDer(smDescDer);
3105  FwSmReleaseDer(esmDescDer);
3106  FwSmReleaseRec(smDescBase);
3107  return smTestCaseFailure;
3108  }
3109  if ((fwSm_logMarker[0]!=2) || (fwSm_logMarker[1]!=12)|| (fwSm_logMarker[2]!=13) || (fwSm_logMarker[3]!=3) ||
3110  (fwSm_logMarker[4]!=4) || (fwSm_logMarker[5]!=1)) {
3111  FwSmReleaseDer(smDescDer);
3112  FwSmReleaseDer(esmDescDer);
3113  FwSmReleaseRec(smDescBase);
3114  return smTestCaseFailure;
3115  }
3116  if ((fwSm_logState[0]!=2) || (fwSm_logState[1]!=12)|| (fwSm_logState[2]!=12) ||
3117  (fwSm_logState[3]!=2) || (fwSm_logState[4]!=2) || (fwSm_logState[5]!=1)) {
3118  FwSmReleaseDer(smDescDer);
3119  FwSmReleaseDer(esmDescDer);
3120  FwSmReleaseRec(smDescBase);
3121  return smTestCaseFailure;
3122  }
3123 
3124  FwSmReleaseDer(smDescDer);
3125  FwSmReleaseDer(esmDescDer);
3126  FwSmReleaseRec(smDescBase);
3127  return smTestCaseSuccess;
3128 }
3129 
3130 /*------------------------------------------------------------------------------------------------- */
3132  struct TestSmData sSmData;
3133  struct TestSmData* smData = &sSmData;
3134  FwSmDesc_t smDescBase, smDescDer;
3135  FwSmAction_t dummyAct1;
3136  FwSmAction_t dummyAct2;
3137  FwSmGuard_t dummyGuard1;
3138  FwSmGuard_t dummyGuard2;
3139 
3140  /* reset log */
3141  fwSm_logIndex = 0;
3142 
3143  /* Initialize data structures for the base state machine SM1 */
3144  smData->counter_1 = 0;
3145  smData->counter_2 = 0;
3146  smData->flag_1 = 0;
3147  smData->flag_2 = 0;
3148  smData->logBase = 0;
3149 
3150  /* Create the base state machine */
3151  smDescBase = FwSmMakeTestSM1(smData);
3152  if (smDescBase==NULL)
3153  return smTestCaseFailure;
3154 
3155  /* Check configuration of base state machine */
3156  if (FwSmCheck(smDescBase) != smSuccess) {
3157  FwSmRelease(smDescBase);
3158  return smTestCaseFailure;
3159  }
3160 
3161  /* Create the derived state machine */
3162  smDescDer = FwSmCreateDer(smDescBase);
3163 
3164  /* Attempt to override a non-existent action and check that an error is reported */
3165  dummyAct1 = (FwSmAction_t)1111;
3166  dummyAct2 = (FwSmAction_t)2222;
3167  FwSmOverrideAction(smDescDer, dummyAct1, dummyAct2);
3168  if (FwSmGetErrCode(smDescDer) != smUndefAction) {
3169  FwSmRelease(smDescBase);
3170  FwSmReleaseDer(smDescDer);
3171  return smTestCaseFailure;
3172  }
3173 
3174  /* Attempt to override a non-existent guard and check that an error is reported */
3175  dummyGuard1 = (FwSmGuard_t)1111;
3176  dummyGuard2 = (FwSmGuard_t)2222;
3177  FwSmOverrideGuard(smDescDer, dummyGuard1, dummyGuard2);
3178  if (FwSmGetErrCode(smDescDer) != smUndefGuard) {
3179  FwSmRelease(smDescBase);
3180  FwSmReleaseDer(smDescDer);
3181  return smTestCaseFailure;
3182  }
3183 
3184  /* Attempt to override an action of a non-derived SM and check that an error is reported */
3185  FwSmOverrideAction(smDescBase, dummyAct1, dummyAct2);
3186  if (FwSmGetErrCode(smDescBase) != smNotDerivedSM) {
3187  FwSmRelease(smDescBase);
3188  FwSmReleaseDer(smDescDer);
3189  return smTestCaseFailure;
3190  }
3191 
3192  /* Attempt to override a guard of a non-derived SM and check that an error is reported */
3193  FwSmOverrideGuard(smDescBase, dummyGuard1, dummyGuard2);
3194  if (FwSmGetErrCode(smDescBase) != smNotDerivedSM) {
3195  FwSmRelease(smDescBase);
3196  FwSmReleaseDer(smDescDer);
3197  return smTestCaseFailure;
3198  }
3199 
3200  FwSmRelease(smDescBase);
3201  FwSmReleaseDer(smDescDer);
3202  return smTestCaseSuccess;
3203 }
3204 
3205 /*------------------------------------------------------------------------------------------------- */
3207  struct TestSmData sSmData;
3208  struct TestSmData* smData = &sSmData;
3209  FwSmDesc_t smDescBase, smDescDer, esmDesc;
3210 
3211  /* reset log */
3212  fwSm_logIndex = 0;
3213 
3214  /* Initialize data structures for the base state machine SM1 */
3215  smData->counter_1 = 0;
3216  smData->counter_2 = 0;
3217  smData->flag_1 = 0;
3218  smData->flag_2 = 0;
3219  smData->logBase = 0;
3220 
3221  /* Create the base state machine */
3222  smDescBase = FwSmMakeTestSM1(smData);
3223  if (smDescBase==NULL)
3224  return smTestCaseFailure;
3225 
3226  /* Check configuration of base state machine */
3227  if (FwSmCheck(smDescBase) != smSuccess) {
3228  FwSmRelease(smDescBase);
3229  return smTestCaseFailure;
3230  }
3231 
3232  /* Create the derived state machine */
3233  smDescDer = FwSmCreateDer(smDescBase);
3234 
3235  /* Create the embedded state machine */
3236  esmDesc = FwSmMakeTestSM1(NULL);
3237 
3238  /* Embed the state machine in state S1 */
3239  FwSmEmbed(smDescDer, STATE_S1, esmDesc);
3240  if (FwSmGetErrCode(smDescDer) != smSuccess) {
3241  FwSmRelease(smDescBase);
3242  FwSmRelease(esmDesc);
3243  FwSmReleaseDer(smDescDer);
3244  return smTestCaseFailure;
3245  }
3246 
3247  /* Embed the state machine in state S1 a second time */
3248  FwSmEmbed(smDescDer, STATE_S1, esmDesc);
3249  if (FwSmGetErrCode(smDescDer) != smEsmDefined) {
3250  FwSmRelease(smDescBase);
3251  FwSmRelease(esmDesc);
3252  FwSmReleaseDer(smDescDer);
3253  return smTestCaseFailure;
3254  }
3255 
3256  /* Attempt to embed the state machine in a base state machine */
3257  FwSmEmbed(smDescBase, 1, esmDesc);
3258  if (FwSmGetErrCode(smDescBase) != smNotDerivedSM) {
3259  FwSmRelease(smDescBase);
3260  FwSmRelease(esmDesc);
3261  FwSmReleaseDer(smDescDer);
3262  return smTestCaseFailure;
3263  }
3264 
3265  /* Attempt to embed the state machine in a non-existent state */
3266  FwSmEmbed(smDescDer, 0, esmDesc);
3267  if (FwSmGetErrCode(smDescDer) != smIllStateId) {
3268  FwSmRelease(smDescBase);
3269  FwSmRelease(esmDesc);
3270  FwSmReleaseDer(smDescDer);
3271  return smTestCaseFailure;
3272  }
3273 
3274  smDescDer->errCode = smSuccess; /* Reset error code */
3275 
3276  FwSmEmbed(smDescDer, 2, esmDesc);
3277  if (FwSmGetErrCode(smDescDer) != smIllStateId) {
3278  FwSmRelease(smDescBase);
3279  FwSmRelease(esmDesc);
3280  FwSmReleaseDer(smDescDer);
3281  return smTestCaseFailure;
3282  }
3283 
3284  FwSmRelease(esmDesc);
3285  FwSmRelease(smDescBase);
3286  FwSmReleaseDer(smDescDer);
3287  return smTestCaseSuccess;
3288 }
3289 
3290 /*------------------------------------------------------------------------------------------------- */
3292  struct TestSmData sSmData;
3293  struct TestSmData* smData = &sSmData;
3294  FwSmDesc_t smDesc;
3295 
3296  /* reset log */
3297  fwSm_logIndex = 0;
3298 
3299  /* Initialize data structures for the base state machine SM1 */
3300  smData->counter_1 = 0;
3301  smData->counter_2 = 0;
3302  smData->flag_1 = 0;
3303  smData->flag_2 = 1;
3304  smData->logBase = 0;
3305 
3306  /* Create the state machine */
3307  smDesc = FwSmMakeTestSM14(smData);
3308  if (smDesc==NULL)
3309  return smTestCaseFailure;
3310 
3311  /* Check configuration of state machine */
3312  if (FwSmCheck(smDesc) != smSuccess) {
3313  FwSmRelease(smDesc);
3314  return smTestCaseFailure;
3315  }
3316 
3317  /* Start SM (this brings it to state S2) */
3318  FwSmStart(smDesc);
3319  if ((smData->counter_2!=2) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3320  FwSmRelease(smDesc);
3321  return smTestCaseFailure;
3322  }
3323 
3324  /* Send transition command TR1 to state machine (this has no effect) */
3325  FwSmMakeTrans(smDesc, TR1);
3326  if ((smData->counter_2!=2) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3327  FwSmRelease(smDesc);
3328  return smTestCaseFailure;
3329  }
3330 
3331  /* Send transition command TR2 to state machine (this terminates it) */
3332  FwSmMakeTrans(smDesc, TR2);
3333  if ((smData->counter_2!=4) || (FwSmGetCurState(smDesc)!=0)) {
3334  FwSmRelease(smDesc);
3335  return smTestCaseFailure;
3336  }
3337 
3338  FwSmRelease(smDesc);
3339  return smTestCaseSuccess;
3340 }
3341 
3342 /*------------------------------------------------------------------------------------------------- */
3344  struct TestSmData sSmData;
3345  struct TestSmData* smData = &sSmData;
3346  FwSmDesc_t smDescBase, smDescDer;
3347 
3348  /* Instantiate the derived state machine */
3349  FW_SM_INST_DER(sSmDescDer, 2, 4, 2)
3350  smDescDer = &sSmDescDer;
3351 
3352  /* reset log */
3353  fwSm_logIndex = 0;
3354 
3355  /* Initialize data structures for the base state machine SM5 */
3356  smData->counter_1 = 0;
3357  smData->counter_2 = 0;
3358  smData->flag_1 = 1;
3359  smData->flag_2 = 0;
3360  smData->logBase = 0;
3361 
3362  /* Create the base state machine */
3363  smDescBase = FwSmMakeTestSM5(NULL);
3364  if (smDescBase==NULL)
3365  return smTestCaseFailure;
3366 
3367  /* Check configuration of base state machine */
3368  if (FwSmCheckRec(smDescBase) != smSuccess) {
3369  FwSmReleaseRec(smDescBase);
3370  return smTestCaseFailure;
3371  }
3372 
3373  /* Initialize the derived state machine */
3374  FwSmInitDer(smDescDer, smDescBase);
3375 
3376  /* Set the data structure for the derived state machine */
3377  FwSmSetData(smDescDer, smData);
3378 
3379  /* Check configuration of derived state machine */
3380  if (FwSmCheckRec(smDescDer) != smSuccess) {
3381  FwSmRelease(smDescBase);
3382  return smTestCaseFailure;
3383  }
3384 
3385  /* Start SM (this brings it to state S1) */
3386  FwSmStart(smDescDer);
3387  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3388  FwSmRelease(smDescBase);
3389  return smTestCaseFailure;
3390  }
3391 
3392  /* Send transition command TR4 to SM and check that this has no effect */
3393  fwSm_logIndex = 0;
3394  FwSmMakeTrans(smDescDer, TR4);
3395  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1) || (fwSm_logIndex!=0)) {
3396  FwSmRelease(smDescBase);
3397  return smTestCaseFailure;
3398  }
3399 
3400  /* Set guard to prevent transition TR2 from S1 to S2 and then check that transition does not take place */
3401  smData->flag_1 = 0;
3402  FwSmMakeTrans(smDescDer, TR2);
3403  if ((smData->counter_1!=1) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1) || (fwSm_logIndex!=0)) {
3404  FwSmRelease(smDescBase);
3405  return smTestCaseFailure;
3406  }
3407 
3408  /* Set guard to allow transition TR2 from S1 to S2 and then check that transition does take place */
3409  smData->flag_1 = 1;
3410  FwSmMakeTrans(smDescDer, TR2);
3411  if ((smData->counter_1!=6) || (smData->counter_2!=2) || (FwSmGetCurState(smDescDer)!=STATE_S2) || (fwSm_logIndex!=3)) {
3412  FwSmRelease(smDescBase);
3413  return smTestCaseFailure;
3414  }
3415  if ((fwSm_logMarker[0]!=3) || (fwSm_logMarker[1]!=4) || (fwSm_logMarker[2]!=1)) {
3416  FwSmRelease(smDescBase);
3417  return smTestCaseFailure;
3418  }
3419 
3420  FwSmRelease(smDescBase);
3421  return smTestCaseSuccess;
3422 }
3423 
3424 /*------------------------------------------------------------------------------------------------- */
3426  struct TestSmData sSmData;
3427  struct TestSmData* smData = &sSmData;
3428  FwSmDesc_t smDescBase;
3429 
3430  /* Instantiate the first derived state machine (this one has the wrong
3431  * number of actions - 3 instead of 4)
3432  */
3433  FW_SM_INST_DER(sSmDescDer1, 2, 3, 2)
3434  FwSmDesc_t smDescDer1 = &sSmDescDer1;
3435 
3436  /* Instantiate the second derived state machine (this one has the wrong
3437  * number of guards - 3 instead of 2)
3438  */
3439  FW_SM_INST_DER(sSmDescDer2, 2, 4, 3)
3440  FwSmDesc_t smDescDer2 = &sSmDescDer2;
3441 
3442 
3443  /* Initialize data structures for the base state machine SM5 */
3444  smData->counter_1 = 0;
3445  smData->counter_2 = 0;
3446  smData->flag_1 = 1;
3447  smData->flag_2 = 0;
3448  smData->logBase = 0;
3449 
3450  /* Create the base state machine */
3451  smDescBase = FwSmMakeTestSM5(NULL);
3452  if (smDescBase==NULL)
3453  return smTestCaseFailure;
3454 
3455  /* Check configuration of base state machine */
3456  if (FwSmCheckRec(smDescBase) != smSuccess) {
3457  FwSmReleaseRec(smDescBase);
3458  return smTestCaseFailure;
3459  }
3460 
3461  /* Try to initialize the first derived state machine and
3462  * check that an error is reported
3463  */
3464  FwSmInitDer(smDescDer1, smDescBase);
3465  if (FwSmGetErrCode(smDescDer1) != smWrongNOfActions) {
3466  FwSmRelease(smDescBase);
3467  return smTestCaseFailure;
3468  }
3469 
3470  /* Try to initialize the second derived state machine and
3471  * check that an error is reported
3472  */
3473  FwSmInitDer(smDescDer2, smDescBase);
3474  if (FwSmGetErrCode(smDescDer2) != smWrongNOfGuards) {
3475  FwSmRelease(smDescBase);
3476  return smTestCaseFailure;
3477  }
3478 
3479  FwSmRelease(smDescBase);
3480  return smTestCaseSuccess;
3481 }
3482 
3483 /*------------------------------------------------------------------------------------------------- */
3485  struct TestSmData sSmData;
3486  struct TestSmData* smData = &sSmData;
3487  FwSmDesc_t smDescBase, smDescDer;
3488 
3489  /* reset log */
3490  fwSm_logIndex = 0;
3491 
3492  /* Initialize data structures for the base state machine SM1 */
3493  smData->counter_1 = 0;
3494  smData->counter_2 = 0;
3495  smData->flag_1 = 0;
3496  smData->flag_2 = 0;
3497  smData->logBase = 0;
3498 
3499  /* Create the base state machine */
3500  smDescBase = FwSmMakeTestSM1(smData);
3501  if (smDescBase==NULL)
3502  return smTestCaseFailure;
3503 
3504  /* Check configuration of base state machine */
3505  if (FwSmCheckRec(smDescBase) != smSuccess) {
3506  FwSmReleaseRec(smDescBase);
3507  return smTestCaseFailure;
3508  }
3509 
3510  /* Create the derived state machine */
3511  smDescDer = FwSmMakeTestSMDer1Static(smDescBase, smData);
3512 
3513  /* Check configuration of derived state machine */
3514  if (FwSmCheck(smDescDer) != smSuccess) {
3515  FwSmRelease(smDescBase);
3516  return smTestCaseFailure;
3517  }
3518 
3519  /* Start SM (this brings it to state S1) */
3520  FwSmStart(smDescDer);
3521  if ((smData->counter_1!=8) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3522  FwSmRelease(smDescBase);
3523  return smTestCaseFailure;
3524  }
3525 
3526  /* Execute state machine twice and check success */
3527  FwSmMakeTrans(smDescDer, FW_TR_EXECUTE);
3528  if ((smData->counter_1!=10) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3529  FwSmRelease(smDescBase);
3530  return smTestCaseFailure;
3531  }
3532 
3533  FwSmMakeTrans(smDescDer, FW_TR_EXECUTE);
3534  if ((smData->counter_1!=12) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3535  FwSmRelease(smDescBase);
3536  return smTestCaseFailure;
3537  }
3538 
3539  /* Command transition from S1 to FPS and check that nothing happens (guard is not true) */
3540  FwSmMakeTrans(smDescDer, TR_S1_FPS);
3541  if ((smData->counter_1!=12) || (smData->counter_2!=1) || (FwSmGetCurState(smDescDer)!=STATE_S1)) {
3542  FwSmRelease(smDescBase);
3543  return smTestCaseFailure;
3544  }
3545 
3546  /* Command transition from S1 to FPS and check that transition is executed (guard is true) */
3547  smData->flag_2 = 1;
3548  FwSmMakeTrans(smDescDer, TR_S1_FPS);
3549  if ((smData->counter_1!=12) || (smData->counter_2!=2) || (FwSmGetCurState(smDescDer)!=0)) {
3550  FwSmRelease(smDescBase);
3551  return smTestCaseFailure;
3552  }
3553 
3554  FwSmRelease(smDescBase);
3555  return smTestCaseSuccess;
3556 }
3557 
3558 /*------------------------------------------------------------------------------------------------- */
3560  struct TestSmData sSmData;
3561  struct TestSmData* smData = &sSmData;
3562  FwSmDesc_t smDesc;
3563 
3564  /* reset log */
3565  fwSm_logIndex = 0;
3566 
3567  /* Initialize data structure holding the state machine data */
3568  smData->counter_1 = 0;
3569  smData->counter_2 = 0;
3570  smData->flag_1 = 0;
3571  smData->flag_2 = 0;
3572  smData->logBase = 0;
3573 
3574  /* Create the test SM */
3575  smDesc = FwSmMakeTestSM13(smData);
3576  if (smDesc==NULL)
3577  return smTestCaseFailure;
3578 
3579  /* Check configuration of state machine */
3580  if (FwSmCheck(smDesc) != smSuccess) {
3581  FwSmRelease(smDesc);
3582  return smTestCaseFailure;
3583  }
3584 
3585  /* Try re-defining state S1 and check that an error is reported */
3586  FwSmAddState(smDesc, STATE_S1, 2, NULL, NULL, NULL, NULL);
3587  if (FwSmGetErrCode(smDesc) != smStateIdInUse) {
3588  FwSmRelease(smDesc);
3589  return smTestCaseFailure;
3590  }
3591 
3592  /* Try adding a new state and check that an error is reported */
3593  FwSmAddState(smDesc, STATE_S2, 2, NULL, NULL, NULL, NULL);
3594  if (FwSmGetErrCode(smDesc) != smIllStateId) {
3595  FwSmRelease(smDesc);
3596  return smTestCaseFailure;
3597  }
3598 
3599  /* Try re-defining choice pseudo-state CPS1 and check that an error is reported */
3600  FwSmAddChoicePseudoState(smDesc, CPS1, 2);
3601  if (FwSmGetErrCode(smDesc) != smChoiceIdInUse) {
3602  FwSmRelease(smDesc);
3603  return smTestCaseFailure;
3604  }
3605 
3606  /* Try adding a new choice pseudo-state and check that an error is reported */
3607  FwSmAddChoicePseudoState(smDesc, CPS2, 2);
3608  if (FwSmGetErrCode(smDesc) != smIllChoiceId) {
3609  FwSmRelease(smDesc);
3610  return smTestCaseFailure;
3611  }
3612 
3613  /* Try adding a new transition and check that an error is reported */
3614  FwSmAddTransStaToSta(smDesc, FW_TR_EXECUTE, STATE_S1, STATE_S1, NULL, NULL);
3615  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
3616  FwSmRelease(smDesc);
3617  return smTestCaseFailure;
3618  }
3619 
3620  /* Try re-defining an existing transition and check that an error is reported */
3621  FwSmAddTransStaToCps(smDesc, FW_TR_EXECUTE, STATE_S1, CPS1, NULL, NULL);
3622  if (FwSmGetErrCode(smDesc) != smTooManyTrans) {
3623  FwSmRelease(smDesc);
3624  return smTestCaseFailure;
3625  }
3626 
3627  FwSmRelease(smDesc);
3628  return smTestCaseSuccess;
3629 }
3630 
3631 /*------------------------------------------------------------------------------------------------- */
3633  struct TestSmData sSmDataBase;
3634  struct TestSmData* smDataBase = &sSmDataBase;
3635  struct TestSmData sEsmDataBase;
3636  struct TestSmData* esmDataBase = &sEsmDataBase;
3637  FwSmDesc_t smDescBase, smDescDer, esmDescDer;
3638 
3639  /* reset log */
3640  fwSm_logIndex = 0;
3641 
3642  /* Create the base state machine */
3643  smDescBase = FwSmMakeTestSM6(smDataBase, esmDataBase);
3644  if (smDescBase==NULL)
3645  return smTestCaseFailure;
3646 
3647  /* Check configuration of base state machine */
3648  if (FwSmCheckRec(smDescBase) != smSuccess) {
3649  FwSmReleaseRec(smDescBase);
3650  return smTestCaseFailure;
3651  }
3652 
3653  /* Start the base state machine */
3654  FwSmStart(smDescBase);
3655 
3656  /* Force the error code of the base SM to a non-nominal value */
3657  smDescBase->errCode = smConfigErr;
3658 
3659  /* Create the derived state machine */
3660  smDescDer = FwSmCreateDer(smDescBase);
3661 
3662  /* Get the SM embedded in state S2 of the derived SM */
3663  esmDescDer = FwSmGetEmbSm(smDescDer,2);
3664 
3665  /* check that derived SM is a clone of base SM */
3666  if (!IsClone(smDescBase, smDescDer)) {
3667  FwSmReleaseDer(smDescDer);
3668  FwSmReleaseDer(esmDescDer);
3669  FwSmReleaseRec(smDescBase);
3670  return smTestCaseFailure;
3671  }
3672 
3673  /* Check the initial state of the derived state machine */
3674  if (FwSmIsStarted(smDescDer) == 1) {
3675  FwSmReleaseDer(smDescDer);
3676  FwSmReleaseDer(esmDescDer);
3677  FwSmReleaseRec(smDescBase);
3678  return smTestCaseFailure;
3679  }
3680 
3681  /* Check the initial value of the error code of the derived state machine */
3682  if (FwSmGetErrCode(smDescDer) != smConfigErr) {
3683  FwSmReleaseDer(smDescDer);
3684  FwSmReleaseDer(esmDescDer);
3685  FwSmReleaseRec(smDescBase);
3686  return smTestCaseFailure;
3687  }
3688 
3689  FwSmReleaseDer(smDescDer);
3690  FwSmReleaseDer(esmDescDer);
3691  FwSmReleaseRec(smDescBase);
3692  return smTestCaseSuccess;
3693 }
3694 
3695 /*------------------------------------------------------------------------------------------------- */
3697  struct TestSmData sSmData;
3698  struct TestSmData* smData = &sSmData;
3699  FwSmDesc_t smDescBase, smDescDer;
3700 
3701  /* Instantiate the derived state machine */
3702  FW_SM_INST_DER(sSmDescDer, 2, 4, 2)
3703  smDescDer = &sSmDescDer;
3704 
3705  /* reset log */
3706  fwSm_logIndex = 0;
3707 
3708  /* Initialize data structures for the base state machine SM5 */
3709  smData->counter_1 = 0;
3710  smData->counter_2 = 0;
3711  smData->flag_1 = 1;
3712  smData->flag_2 = 0;
3713  smData->logBase = 0;
3714 
3715  /* Create the base state machine */
3716  smDescBase = FwSmMakeTestSM5(NULL);
3717  if (smDescBase==NULL)
3718  return smTestCaseFailure;
3719 
3720  /* Check configuration of base state machine */
3721  if (FwSmCheckRec(smDescBase) != smSuccess) {
3722  FwSmReleaseRec(smDescBase);
3723  return smTestCaseFailure;
3724  }
3725 
3726  /* Force the error code of the base SM to a non-nominal value */
3727  smDescBase->errCode = smConfigErr;
3728 
3729  /* Initialize the derived state machine */
3730  FwSmInitDer(smDescDer, smDescBase);
3731 
3732  /* check that derived SM is a clone of base SM */
3733  if (!IsClone(smDescBase, smDescDer)) {
3734  FwSmReleaseRec(smDescBase);
3735  return smTestCaseFailure;
3736  }
3737 
3738  /* Check the initial state of the derived state machine */
3739  if (FwSmIsStarted(smDescDer) == 1) {
3740  FwSmReleaseRec(smDescBase);
3741  return smTestCaseFailure;
3742  }
3743 
3744  /* Check the initial value of the error code of the derived state machine */
3745  if (FwSmGetErrCode(smDescDer) != smConfigErr) {
3746  FwSmReleaseRec(smDescBase);
3747  return smTestCaseFailure;
3748  }
3749 
3750  FwSmReleaseRec(smDescBase);
3751  return smTestCaseSuccess;
3752 }
3753 
3754 /*------------------------------------------------------------------------------------------------- */
3756  struct TestSmData sSmData;
3757  struct TestSmData* smData = &sSmData;
3758  FwSmDesc_t smDesc;
3759 
3760  /* reset log */
3761  fwSm_logIndex = 0;
3762 
3763  /* Initialize data structure holding the state machine data */
3764  smData->counter_1 = 0;
3765  smData->counter_2 = 0;
3766  smData->flag_1 = 0;
3767  smData->flag_2 = 0;
3768  smData->logBase = 0;
3769 
3770  /* Create test SM */
3771  smDesc = FwSmMakeTestSM15(smData);
3772  if (smDesc==NULL)
3773  return smTestCaseFailure;
3774 
3775  /* Check configuration of state machine */
3776  if (FwSmCheck(smDesc) != smSuccess) {
3777  FwSmRelease(smDesc);
3778  return smTestCaseFailure;
3779  }
3780 
3781  /* Check initial value of execution counters */
3782  if ((FwSmGetExecCnt(smDesc)!=0) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3783  FwSmRelease(smDesc);
3784  return smTestCaseFailure;
3785  }
3786 
3787  /* Start SM (this brings it to state S1) */
3788  FwSmStart(smDesc);
3789  if ((smData->counter_1!=0) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
3790  FwSmRelease(smDesc);
3791  return smTestCaseFailure;
3792  }
3793 
3794  /* Send command TR1 and check that nothing happens */
3795  FwSmMakeTrans(smDesc,TR1);
3796  if ((smData->counter_1!=0) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
3797  FwSmRelease(smDesc);
3798  return smTestCaseFailure;
3799  }
3800  if ((FwSmGetExecCnt(smDesc)!=0) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3801  FwSmRelease(smDesc);
3802  return smTestCaseFailure;
3803  }
3804 
3805  /* Execute SM and check that it makes a transition to S2 */
3806  FwSmExecute(smDesc);
3807  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3808  FwSmRelease(smDesc);
3809  return smTestCaseFailure;
3810  }
3811  if ((FwSmGetExecCnt(smDesc)!=1) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3812  FwSmRelease(smDesc);
3813  return smTestCaseFailure;
3814  }
3815 
3816  /* Send command TR1 and check that nothing happens */
3817  FwSmMakeTrans(smDesc,TR1);
3818  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3819  FwSmRelease(smDesc);
3820  return smTestCaseFailure;
3821  }
3822  if ((FwSmGetExecCnt(smDesc)!=1) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3823  FwSmRelease(smDesc);
3824  return smTestCaseFailure;
3825  }
3826 
3827  /* Execute SM and check that counters are incremented but SM remains in SM2 */
3828  FwSmExecute(smDesc);
3829  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3830  FwSmRelease(smDesc);
3831  return smTestCaseFailure;
3832  }
3833  if ((FwSmGetExecCnt(smDesc)!=2) || (FwSmGetStateExecCnt(smDesc)!=1)) {
3834  FwSmRelease(smDesc);
3835  return smTestCaseFailure;
3836  }
3837 
3838  /* Send command TR1 and check that nothing happens */
3839  FwSmMakeTrans(smDesc,TR1);
3840  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3841  FwSmRelease(smDesc);
3842  return smTestCaseFailure;
3843  }
3844  if ((FwSmGetExecCnt(smDesc)!=2) || (FwSmGetStateExecCnt(smDesc)!=1)) {
3845  FwSmRelease(smDesc);
3846  return smTestCaseFailure;
3847  }
3848 
3849  /* Execute SM and check that counters are incremented but SM remains in SM2 */
3850  FwSmExecute(smDesc);
3851  if ((smData->counter_1!=1) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S2)) {
3852  FwSmRelease(smDesc);
3853  return smTestCaseFailure;
3854  }
3855  if ((FwSmGetExecCnt(smDesc)!=3) || (FwSmGetStateExecCnt(smDesc)!=2)) {
3856  FwSmRelease(smDesc);
3857  return smTestCaseFailure;
3858  }
3859 
3860  /* Send command TR1 and check that SM moves to S1 */
3861  FwSmMakeTrans(smDesc,TR1);
3862  if ((smData->counter_1!=3) || (smData->counter_2!=0) || (FwSmGetCurState(smDesc)!=STATE_S1)) {
3863  FwSmRelease(smDesc);
3864  return smTestCaseFailure;
3865  }
3866  if ((FwSmGetExecCnt(smDesc)!=3) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3867  FwSmRelease(smDesc);
3868  return smTestCaseFailure;
3869  }
3870 
3871  /* Execute SM and check that SM is stopped but counters are not reset */
3872  FwSmExecute(smDesc);
3873  if ((smData->counter_1!=3) || (smData->counter_2!=0) || (FwSmIsStarted(smDesc)!=0)) {
3874  FwSmRelease(smDesc);
3875  return smTestCaseFailure;
3876  }
3877  if ((FwSmGetExecCnt(smDesc)!=4) || (FwSmGetStateExecCnt(smDesc)!=1)) {
3878  FwSmRelease(smDesc);
3879  return smTestCaseFailure;
3880  }
3881 
3882  /* Restart SM and check that counters are reset */
3883  FwSmStart(smDesc);
3884  if ((FwSmGetExecCnt(smDesc)!=0) || (FwSmGetStateExecCnt(smDesc)!=0)) {
3885  FwSmRelease(smDesc);
3886  return smTestCaseFailure;
3887  }
3888 
3889  FwSmRelease(smDesc);
3890  return smTestCaseSuccess;
3891 
3892 }
3893 
3894 /*------------------------------------------------------------------------------------------------- */
3896  struct TestSmData sSmData;
3897  struct TestSmData* smData = &sSmData;
3898  FwSmDesc_t smDescBase, smDescDer;
3899 
3900  /* reset log */
3901  fwSm_logIndex = 0;
3902 
3903  /* Initialize data structures for the base state machine SM5 */
3904  smData->counter_1 = 0;
3905  smData->counter_2 = 0;
3906  smData->flag_1 = 1;
3907  smData->flag_2 = 0;
3908  smData->logBase = 0;
3909 
3910  /* Create the base state machine */
3911  smDescBase = FwSmMakeTestSM11(NULL);
3912  if (smDescBase==NULL)
3913  return smTestCaseFailure;
3914 
3915  /* Check configuration of base state machine */
3916  if (FwSmCheckRec(smDescBase) != smSuccess) {
3917  return smTestCaseFailure;
3918  }
3919 
3920  /* Create the derived state machine */
3921  smDescDer = FwSmCreateDer(smDescBase);
3922 
3923  /* Set the data structure for the derived state machine */
3924  FwSmSetData(smDescDer, smData);
3925 
3926  /* Check configuration of derived state machine */
3927  if (FwSmCheckRec(smDescDer) != smSuccess) {
3928  FwSmRelease(smDescBase);
3929  FwSmReleaseDer(smDescDer);
3930  return smTestCaseFailure;
3931  }
3932 
3933  /* Start SM (this causes the SM to terminate) */
3934  FwSmStart(smDescDer);
3935  if ((smData->counter_2!=1) || (FwSmIsStarted(smDescDer)!=0)) {
3936  FwSmRelease(smDescBase);
3937  FwSmReleaseDer(smDescDer);
3938  return smTestCaseFailure;
3939  }
3940 
3941  FwSmReleaseDer(smDescDer);
3942  return smTestCaseSuccess;
3943 }
3944 
3945 /*------------------------------------------------------------------------------------------------- */
3947  struct TestSmData sSmData;
3948  struct TestSmData* smData = &sSmData;
3949  FwSmDesc_t smDesc1, smDesc2, smDesc3;
3950 
3951  /* reset log */
3952  fwSm_logIndex = 0;
3953 
3954  /* Initialize data structure holding the state machine data */
3955  smData->counter_1 = 0;
3956  smData->counter_2 = 0;
3957  smData->flag_1 = 1;
3958  smData->flag_2 = 1;
3959  smData->flag_3 = 1;
3960  smData->logBase = 0;
3961 
3962  /* Create test SMs */
3963  smDesc1 = FwSmMakeTestSM16_1(smData);
3964  smDesc2 = FwSmMakeTestSM16_2(smData);
3965  smDesc3 = FwSmMakeTestSM16_3(smData);
3966 
3967  /* Check configuration of state machine */
3968  if ((FwSmCheck(smDesc1) != smSuccess) || (FwSmCheck(smDesc2) != smSuccess) ||
3969  (FwSmCheck(smDesc3) != smSuccess)) {
3970  FwSmRelease(smDesc1);
3971  FwSmRelease(smDesc2);
3972  FwSmRelease(smDesc3);
3973  return smTestCaseFailure;
3974  }
3975 
3976  /* Start SM and check outcome of start operation */
3977  FwSmStart(smDesc1);
3978  FwSmStart(smDesc2);
3979  FwSmStart(smDesc3);
3980  if ((FwSmGetCurState(smDesc1)!=STATE_S1) || (FwSmGetCurState(smDesc2)!=STATE_S1) ||
3981  (FwSmGetCurState(smDesc3)!=STATE_S1)){
3982  FwSmRelease(smDesc1);
3983  FwSmRelease(smDesc2);
3984  FwSmRelease(smDesc3);
3985  return smTestCaseFailure;
3986  }
3987 
3988  /* Send TR1 and check success */
3989  FwSmMakeTrans(smDesc1, TR1);
3990  FwSmMakeTrans(smDesc2, TR1);
3991  FwSmMakeTrans(smDesc3, TR1);
3992  if ((FwSmGetCurState(smDesc1)!=STATE_S2) || (FwSmGetCurState(smDesc2)!=STATE_S4) ||
3993  (FwSmGetCurState(smDesc3)!=STATE_S3)){
3994  FwSmRelease(smDesc1);
3995  FwSmRelease(smDesc2);
3996  FwSmRelease(smDesc3);
3997  return smTestCaseFailure;
3998  }
3999 
4000  /* Stop and Restart SM and check outcome of start operation */
4001  FwSmStop(smDesc1);
4002  FwSmStop(smDesc2);
4003  FwSmStop(smDesc3);
4004  FwSmStart(smDesc1);
4005  FwSmStart(smDesc2);
4006  FwSmStart(smDesc3);
4007  if ((FwSmGetCurState(smDesc1)!=STATE_S1) || (FwSmGetCurState(smDesc2)!=STATE_S1) ||
4008  (FwSmGetCurState(smDesc3)!=STATE_S1)){
4009  FwSmRelease(smDesc1);
4010  FwSmRelease(smDesc2);
4011  FwSmRelease(smDesc3);
4012  return smTestCaseFailure;
4013  }
4014 
4015  /* Set Flag_1 to false */
4016  smData->flag_1 = 0;
4017 
4018  /* Send TR1 and check success */
4019  FwSmMakeTrans(smDesc1, TR1);
4020  FwSmMakeTrans(smDesc2, TR1);
4021  FwSmMakeTrans(smDesc3, TR1);
4022  if ((FwSmGetCurState(smDesc1)!=STATE_S3) || (FwSmGetCurState(smDesc2)!=STATE_S4) ||
4023  (FwSmGetCurState(smDesc3)!=STATE_S3)){
4024  FwSmRelease(smDesc1);
4025  FwSmRelease(smDesc2);
4026  FwSmRelease(smDesc3);
4027  return smTestCaseFailure;
4028  }
4029 
4030  FwSmRelease(smDesc1);
4031  FwSmRelease(smDesc2);
4032  FwSmRelease(smDesc3);
4033  return smTestCaseSuccess;
4034 }
4035 
4036 /*------------------------------------------------------------------------------------------------- */
4038  struct TestSmData sSmData;
4039  struct TestSmData* smData = &sSmData;
4040  FwSmDesc_t smDesc1, smDesc2, smDesc3;
4041 
4042  /* reset log */
4043  fwSm_logIndex = 0;
4044 
4045  /* Initialize data structure holding the state machine data */
4046  smData->counter_1 = 0;
4047  smData->counter_2 = 0;
4048  smData->flag_1 = 1;
4049  smData->flag_2 = 1;
4050  smData->flag_3 = 1;
4051  smData->logBase = 0;
4052 
4053  /* Create test SMs */
4054  smDesc1 = FwSmMakeTestSM16_1(smData);
4055  smDesc2 = FwSmMakeTestSM16_2(smData);
4056  smDesc3 = FwSmMakeTestSM16_3(smData);
4057 
4058  /* Check configuration of state machine */
4059  if ((FwSmCheck(smDesc1) != smSuccess) || (FwSmCheck(smDesc2) != smSuccess) ||
4060  (FwSmCheck(smDesc3) != smSuccess)) {
4061  FwSmRelease(smDesc1);
4062  FwSmRelease(smDesc2);
4063  FwSmRelease(smDesc3);
4064  return smTestCaseFailure;
4065  }
4066 
4067  /* Start SM and check outcome of start operation */
4068  FwSmStart(smDesc1);
4069  FwSmStart(smDesc2);
4070  FwSmStart(smDesc3);
4071  if ((FwSmGetCurState(smDesc1)!=STATE_S1) || (FwSmGetCurState(smDesc2)!=STATE_S1) ||
4072  (FwSmGetCurState(smDesc3)!=STATE_S1)){
4073  FwSmRelease(smDesc1);
4074  FwSmRelease(smDesc2);
4075  FwSmRelease(smDesc3);
4076  return smTestCaseFailure;
4077  }
4078 
4079  /* Send TR2 and check success */
4080  FwSmMakeTrans(smDesc1, TR2);
4081  FwSmMakeTrans(smDesc2, TR2);
4082  FwSmMakeTrans(smDesc3, TR2);
4083  if ((FwSmGetCurState(smDesc1)!=STATE_S2) || (FwSmGetCurState(smDesc2)!=STATE_S4) ||
4084  (FwSmGetCurState(smDesc3)!=STATE_S3)){
4085  FwSmRelease(smDesc1);
4086  FwSmRelease(smDesc2);
4087  FwSmRelease(smDesc3);
4088  return smTestCaseFailure;
4089  }
4090 
4091  /* Stop and Restart SM and check outcome of start operation */
4092  FwSmStop(smDesc1);
4093  FwSmStop(smDesc2);
4094  FwSmStop(smDesc3);
4095  FwSmStart(smDesc1);
4096  FwSmStart(smDesc2);
4097  FwSmStart(smDesc3);
4098  if ((FwSmGetCurState(smDesc1)!=STATE_S1) || (FwSmGetCurState(smDesc2)!=STATE_S1) ||
4099  (FwSmGetCurState(smDesc3)!=STATE_S1)){
4100  FwSmRelease(smDesc1);
4101  FwSmRelease(smDesc2);
4102  FwSmRelease(smDesc3);
4103  return smTestCaseFailure;
4104  }
4105 
4106  /* Set Flag_1 to false */
4107  smData->flag_1 = 0;
4108 
4109  /* Send TR1 and check success */
4110  FwSmMakeTrans(smDesc1, TR2);
4111  FwSmMakeTrans(smDesc2, TR2);
4112  FwSmMakeTrans(smDesc3, TR2);
4113  if ((FwSmGetCurState(smDesc1)!=STATE_S3) || (FwSmGetCurState(smDesc2)!=STATE_S4) ||
4114  (FwSmGetCurState(smDesc3)!=STATE_S3)){
4115  FwSmRelease(smDesc1);
4116  FwSmRelease(smDesc2);
4117  FwSmRelease(smDesc3);
4118  return smTestCaseFailure;
4119  }
4120 
4121  FwSmRelease(smDesc1);
4122  FwSmRelease(smDesc2);
4123  FwSmRelease(smDesc3);
4124  return smTestCaseSuccess;
4125 }
A choice pseudo-state is added to a state machine with an illegal (out-of-range) identifier.
FwSmBool_t SmDummyGuard(FwSmDesc_t smDesc)
Dummy guard which always returns true.
Definition: FwSmCore.c:46
Declaration of test cases for the FW State Machine Module.
void FwSmAddTransStaToSta(FwSmDesc_t smDesc, FwSmCounterU2_t transId, FwSmCounterS1_t srcId, FwSmCounterS1_t destId, FwSmAction_t trAction, FwSmGuard_t trGuard)
Create a transition from a proper state to a proper state and add it to a state machine.
Definition: FwSmConfig.c:191
FwSmDesc_t FwSmGetEmbSmCur(FwSmDesc_t smDesc)
Return the state machine embedded in the current state.
Definition: FwSmCore.c:208
FwSmDesc_t FwSmMakeTestSM16_1(struct TestSmData *smData)
Operation to create and configure a state machine to verify the order of evaluation of guards...
Definition: FwSmMakeTest.c:792
#define FW_TR_EXECUTE
Identifier of "Execute" transition in a state machine.
FwSmTestOutcome_t FwSmTestCaseDummySM3()
Verify the behaviour of a degenerate state machine which consists of a single direct transition from ...
FwSmTestOutcome_t FwSmTestCaseDer4()
Create a derived state machine by extending state machine SM5 (see FwSmMakeTestSM5) and then verify t...
FwSmTestOutcome_t FwSmTestCaseCheck21()
Configure a state machine to have a state which is not reachable and check that FwSmCheck detects and...
#define LOG_ARRAY_SIZE
Size of the log arrays.
Definition: FwPrMakeTest.h:46
FwSmTestOutcome_t FwSmTestCaseTrans1()
Test a direct transition between two simple states (states S1 and S2 of SM5).
A transition from a certain source (either a state or a choice pseudo-state) is added to a state mach...
FwSmDesc_t FwSmMakeTestSM5(struct TestSmData *smData)
Operation to create and configure the state machine SM5.
Definition: FwSmMakeTest.c:321
FwSmTestOutcome_t FwSmTestCasePrint1()
Verify the ability of the FwSmPrintConfig function to write to a file the configuration of a state ma...
FwSmTestOutcome_t FwSmTestCaseCheck15()
Verify the ability of the state machine creation function FwSmCreate to detect illegal values of its ...
#define TR1
A transition identifier.
Definition: FwSmMakeTest.h:56
Declaration of the dynamical creation interface for a FW State Machine.
FwSmTestOutcome_t FwSmTestCaseCheck17()
Configure a state to exceed the maximum number of actions and check that an error is reported...
void FwSmRelease(FwSmDesc_t smDesc)
Release the memory which was allocated when the state machine descriptor.
Definition: FwSmDCreate.c:201
FwSmBool_t FwSmIsStarted(FwSmDesc_t smDesc)
Check whether the state machine is started.
Definition: FwSmCore.c:240
There is an undefined transition in a state machine.
There is an undefined state in a state machine.
Definition: FwSmConstants.h:94
There is an undefined choice pseudo-state in a state machine.
Definition: FwSmConstants.h:98
FwSmTestOutcome_t FwSmTestCaseDescStatic3()
Create state machine SM1 statically and then check that it behaves correctly.
FwSmCounterS1_t nOfActions
the number of actions (state actions + transition actions) in the state machine
Definition: FwSmPrivate.h:313
FwSmTestOutcome_t FwSmTestCaseJunction1()
Verify the use of a choice pseudo-state acting as a "junction" to join two branches from two differen...
#define CPS2
A choice pseudo-state identifier.
Definition: FwSmMakeTest.h:46
FwSmErrCode_t FwSmGetErrCode(FwSmDesc_t smDesc)
Return the error code of the argument state machine.
Definition: FwSmCore.c:248
int flag_1
Flag checked by the transition guards.
Definition: FwSmMakeTest.h:107
FwSmDesc_t FwSmMakeTestSMDer1Static(FwSmDesc_t smDescBase, struct TestSmData *smData)
Create a derived state machine and override one of its actions and one of its guards.
Definition: FwSmMakeTest.c:771
A configuration error has been detected during the state machine configuration process.
Type for the state machine data for the test state machines.
Definition: FwSmMakeTest.h:101
FwSmAction_t * smActions
the state machine actions (state and transition actions)
Definition: FwSmPrivate.h:307
An error was encountered while executing a transition in a state machine (see FwSmMakeTrans).
void FwSmReleaseDer(FwSmDesc_t smDesc)
Release the memory allocated to a derived state machine descriptor.
Definition: FwSmDCreate.c:223
FwSmDesc_t FwSmMakeTestSM12(struct TestSmData *smData)
Operation to create and configure a state machine where a transition has a choice pseudo-state as bot...
Definition: FwSmMakeTest.c:652
The number of actions added to the state machine is smaller than the number of actions declared when ...
FwSmTestOutcome_t FwSmTestCaseDer5()
Create a derived state machine by extending state machine SM1 (see FwSmMakeTestSM1), override one of its actions and one of its guards, and then verify the correct behaviour of the derived state machine.
FwSmCounterU3_t FwSmGetExecCnt(FwSmDesc_t smDesc)
Return the State Machine Execution Counter.
Definition: FwSmCore.c:253
void FwSmStop(FwSmDesc_t smDesc)
Stop a state machine.
Definition: FwSmCore.c:69
FwSmTestOutcome_t FwSmTestCaseExecute2()
Test the Execute command in a configuration where the command only causes the do-action of a state wi...
#define FW_SM_INST_DER(SM_DESC, NS, NA, NG)
Instantiate a descriptor for a derived state machine.
Definition: FwSmSCreate.h:231
FwSmTestOutcome_t FwSmTestCaseCheck12()
Verify the ability of FwSmCheck to detect and report the configuration error due a transition having ...
FwSmCounterU3_t FwSmGetStateExecCnt(FwSmDesc_t smDesc)
Return the State Execution Counter.
Definition: FwSmCore.c:258
int logBase
Offset for markers written to log array.
Definition: FwSmMakeTest.h:113
FwSmTestOutcome_t FwSmTestCaseDummySM9Static()
Verify the behaviour of a degenerate state machine which has no transitions other than the transition...
#define TR2
A transition identifier.
Definition: FwSmMakeTest.h:58
FwSmTestOutcome_t FwSmTestCaseCheck20()
Configure a state machine to have too few actions and check that FwSmCheck detects and reports this s...
Declaration of the configuration interface for a FW State Machine.
int flag_2
Flag checked by the transition guards.
Definition: FwSmMakeTest.h:109
FwSmDesc_t FwSmCreate(FwSmCounterS1_t nOfStates, FwSmCounterS1_t nOfChoicePseudoStates, FwSmCounterS1_t nOfTrans, FwSmCounterS1_t nOfActions, FwSmCounterS1_t nOfGuards)
Create a new state machine descriptor.
Definition: FwSmDCreate.c:23
FwSmTestOutcome_t FwSmTestCaseDummySM9()
Verify the behaviour of a degenerate state machine which has no transitions other than the transition...
FwSmCounterS1_t nOfPStates
the number of states in the state machine
Definition: FwSmPrivate.h:243
FwSmTestOutcome_t FwSmTestCaseConfigErr1()
Test an application which attempts to perform illegal configuration operations on a State Machine Des...
FwSmTestOutcome_t FwSmTestCaseCheck9()
Verify the ability of the configuration check to detect and report a configuration error in an embedd...
void FwSmAddTransStaToCps(FwSmDesc_t smDesc, FwSmCounterU2_t transId, FwSmCounterS1_t srcId, FwSmCounterS1_t destId, FwSmAction_t trAction, FwSmGuard_t trGuard)
Create a transition from a proper state to a choice pseudo-state and add it to a state machine...
Definition: FwSmConfig.c:197
FwSmTestOutcome_t FwSmTestCaseTrans8()
Verify the order of evaluation of guards on transitions out of a choice pseudo-state.
Declaration of functions to create and configure test state machines.
FwSmTestOutcome_t FwSmTestCaseCheck5()
Verify the ability of FwSmCheck to detect and report the configuration error due an out-going transit...
FwSmDesc_t FwSmMakeTestSM7(struct TestSmData *smData)
Operation to create and configure the state machine SM7.
Definition: FwSmMakeTest.c:504
void FwSmExecute(FwSmDesc_t smDesc)
Convenience method to execute a state machine.
Definition: FwSmCore.c:142
FwSmTestOutcome_t FwSmTestCaseCheck4()
Verify the ability of FwSmCheck to detect and report the configuration error due to initial pseudo-st...
A choice pseudo-state is added to a state machine with less than 1 out-going transitions.
FwSmTestOutcome_t FwSmTestCaseExecute4()
Test propagation of execution command to an ESM.
A transition is added to a state machine with a source (either a state or a choice pseudo-state) whic...
#define STATE_S4
A state identifier.
Definition: FwSmMakeTest.h:42
The number of guards added to the state machine exceeds the number of guards declared when the state ...
FwSmTestOutcome_t FwSmTestCaseConfigErr2()
Configure a state machine and then try to re-configure it and check that the reconfiguration attempt ...
The number of guards in the base state machine is not the same as in the derived state machine...
FwSmTestOutcome_t FwSmTestCaseExecCnt1()
Verify the functioning of the execution counters.
int flag_3
Flag checked by the transition guards.
Definition: FwSmMakeTest.h:111
FwSmTestOutcome_t FwSmTestCaseDer1()
Create a derived state machine by extending state machine SM5 (see FwSmMakeTestSM5) and then verify t...
The number of actions added to the state machine exceeds the number of actions declared when the stat...
FwSmTestOutcome_t FwSmTestCaseStart2()
Test the Start command on a state machine where the initial pseudo-state is connected to a choice pse...
FwSmTestOutcome_t FwSmTestCaseTrans5()
Test a transition from a state to the final pseudo-state passing through a choice pseudo-state...
void FwSmOverrideGuard(FwSmDesc_t smDesc, FwSmGuard_t oldGuard, FwSmGuard_t newGuard)
Override a guard in a derived state machine.
Definition: FwSmConfig.c:475
FwSmErrCode_t errCode
either &#39;success&#39; or the code of the last error encountered by the state machine
Definition: FwSmPrivate.h:325
FwSmTestOutcome_t FwSmTestCaseDerErr1()
Instantiate a derived state machine and try to initialize it with a base state machine with the wrong...
The state machine where an action or a guard is overridden or a state machine is embedded is not a de...
FwSmTestOutcome_t FwSmTestCaseStart3()
Test the Start command on a simple state machine where the initial pseudo-state is directly connected...
FwSmDesc_t FwSmMakeTestSM6(struct TestSmData *smData, struct TestSmData *esmData)
Operation to create and configure the state machine SM6.
Definition: FwSmMakeTest.c:475
void FwSmInitDer(FwSmDesc_t smDesc, FwSmDesc_t smDescBase)
Initialize a state machine descriptor to extend another state machine (the base state machine)...
Definition: FwSmSCreate.c:54
The state machine has a choice pseudo-state which is not a destination of any transition.
int fwSm_logState[LOG_ARRAY_SIZE]
Log array where SM operations write the state of their SM.
Definition: FwSmMakeTest.c:35
#define TR4
A transition identifier.
Definition: FwSmMakeTest.h:62
FwSmTestOutcome_t FwSmTestCaseExecute3()
Test the Execute command in a configuration where the command triggers a transition between two prope...
FwSmErrCode_t FwSmCheckRec(FwSmDesc_t smDesc)
Recursively check the configuration of a state machine and all its embedded state machines...
Definition: FwSmConfig.c:438
FwSmTestOutcome_t FwSmTestCaseCheck10()
Verify the ability of the configuration functions of a state machine to detect and report the followi...
FwSmTestOutcome_t FwSmTestCaseTrans3()
Test propagation of a transition command from an SM to its ESM in a situation where the command has n...
void FwSmAddChoicePseudoState(FwSmDesc_t smDesc, FwSmCounterS1_t choiceId, FwSmCounterS1_t nOfOutTrans)
Create a choice pseudo-state with the given characteristics and add it to a state machine...
Definition: FwSmConfig.c:140
FwSmTestOutcome_t FwSmTestCaseStop2()
Test the Stop command for a state machine with an embedded state machine.
void FwSmOverrideAction(FwSmDesc_t smDesc, FwSmAction_t oldAction, FwSmAction_t newAction)
Override an action (either a state action or a transition action) in a derived state machine...
Definition: FwSmConfig.c:456
FwSmTestOutcome_t FwSmTestCaseDerConfigErr1()
Verify the ability of the configuration operation on a derived state machine to detect and report err...
struct FwSmDesc ** esmDesc
the state machines embedded in the state machine
Definition: FwSmPrivate.h:311
FwSmTestOutcome_t FwSmTestCaseTrans2()
Test a transition through a choice pseudo-state between two simple states (states S1 and S2 of SM5)...
FwSmTestOutcome_t FwSmTestCaseTransErr1()
Test a transition which goes through a choice pseudo-state without any out-going transition with a tr...
FwSmTestOutcome_t FwSmTestCaseDer6()
Create a derived state machine by extending state machine SM11 (see FwSmMakeTestSM11), and then verify the correct behaviour of the derived state machine.
FwSmDesc_t FwSmMakeTestSM1(struct TestSmData *smData)
Operation to create and configure the state machine SM1.
Definition: FwSmMakeTest.c:208
A transition is added to a state machine with an illegal (out-of-range) choice pseudo-state destinati...
FwSmBool_t(* FwSmGuard_t)(FwSmDesc_t)
Type for a pointer to a state machine guard.
Definition: FwSmConstants.h:64
FwSmDesc_t FwSmCreateDer(FwSmDesc_t smDesc)
Create the descriptor of a derived state machine.
Definition: FwSmDCreate.c:137
FwSmTestOutcome_t FwSmTestCaseCheck7()
Verify the ability of the configuration functions of a state machine to detect and report the followi...
FwSmTestOutcome_t FwSmTestCaseCheck2()
Verify the ability of FwSmCheck to detect and report the configuration error due to a choice pseudo-s...
FwSmDesc_t FwSmMakeTestSM11(struct TestSmData *smData)
Operation to create and configure a degenerate state machine with neither states nor choice pseudo-st...
Definition: FwSmMakeTest.c:611
FwSmDesc_t FwSmMakeTestSM5Dir(struct TestSmData *smData)
Operation to create and configure the state machine SM5 (see FwSmMakeTestSM5 and figure below) by dir...
Definition: FwSmMakeTest.c:370
FwSmDesc_t FwSmMakeTestSMDer1(FwSmDesc_t smDescBase, struct TestSmData *smData)
Create a derived state machine and override one of its actions and one of its guards.
Definition: FwSmMakeTest.c:758
FwSmDesc_t FwSmMakeTestSM15(struct TestSmData *smData)
Operation to create and configure a state machine which uses the execution counters.
Definition: FwSmMakeTest.c:732
FwSmTestOutcome_t FwSmTestCaseCheck1()
Verify the ability of FwSmCheck to detect and report the configuration error due to a state in a stat...
A state is added with a negative number of outgoing transitions.
FwSmDesc_t FwSmMakeTestSM1Static(struct TestSmData *smData)
Operation to create and configure the state machine SM1 (see FwSmMakeTestSM1 and figure below) static...
Definition: FwSmMakeTest.c:228
FwSmTestOutcome_t
Outcome of a state machine test case.
Definition: FwSmTestCases.h:23
#define CPS1
A choice pseudo-state identifier.
Definition: FwSmMakeTest.h:44
void(* FwSmAction_t)(FwSmDesc_t)
Type for a pointer to a state machine action.
Definition: FwSmConstants.h:46
The state machine has a state which is not a destination of any transition.
FwSmDesc_t FwSmGetEmbSm(FwSmDesc_t smDesc, FwSmCounterS1_t i)
Return the state machine embedded in the i-th state of the argument state machine.
Definition: FwSmCore.c:217
The overridden guard in a derived state machine does not exist.
void FwSmStart(FwSmDesc_t smDesc)
Start a state machine.
Definition: FwSmCore.c:52
FwSmTestOutcome_t FwSmTestCaseCheck22()
Configure a state machine to have a choice pseudo-state which is not reachable and check that FwSmChe...
int fwSm_logIndex
Index for write operations in log arrays.
Definition: FwSmMakeTest.c:39
#define STATE_S2
A state identifier.
Definition: FwSmMakeTest.h:38
#define STATE_S1
A state identifier.
Definition: FwSmMakeTest.h:36
FwSmTestOutcome_t FwSmTestCaseDerEmbed1()
Verify the ability of the configuration functions of a derived state machines to detect and report er...
void FwSmMakeTrans(FwSmDesc_t smDesc, FwSmCounterU2_t transId)
Trigger a transition in a state machine.
Definition: FwSmCore.c:92
FwSmDesc_t FwSmMakeTestSM5Static(struct TestSmData *smData)
Operation to create and configure the state machine SM5 (see FwSmMakeTestSM5 and figure below) static...
Definition: FwSmMakeTest.c:348
Structure representing a state machine descriptor.
Definition: FwSmPrivate.h:303
FwSmTestOutcome_t FwSmTestCaseDerConfig1()
Create a derived state machine dynamically and then check the configuration of the newly created stat...
FwSmTestOutcome_t FwSmTestCaseStop1()
Test the Stop command on a state machine without embedded state machines.
A choice pseudo-state is added twice to the same state machine.
FwSmDesc_t FwSmMakeTestSM8(struct TestSmData *smData)
Operation to create and configure a degenerate state machine with no states.
Definition: FwSmMakeTest.c:527
FwSmDesc_t FwSmMakeTestSM10(struct TestSmData *smData, struct TestSmData *esmData)
Operation to create and configure the state machine SM10.
Definition: FwSmMakeTest.c:581
FwSmTestOutcome_t FwSmTestCaseTrans6()
Test a transition from one state to another state with an embedded state machine. ...
FwSmDesc_t FwSmMakeTestSM3(struct TestSmData *smData, struct TestSmData *esmData)
Operation to create and configure the state machine SM3.
Definition: FwSmMakeTest.c:266
void FwSmAddTransIpsToCps(FwSmDesc_t smDesc, FwSmCounterS1_t destId, FwSmAction_t trAction)
Create a transition from the initial pseudo-state to a choice pseudo-state and add it to a state mach...
Definition: FwSmConfig.c:186
void FwSmAddTransCpsToFps(FwSmDesc_t smDesc, FwSmCounterS1_t srcId, FwSmAction_t trAction, FwSmGuard_t trGuard)
Create a transition from a choice pseudo-state to the final pseudo-state and add it to a state machin...
Definition: FwSmConfig.c:215
FwSmCounterS1_t FwSmGetCurState(FwSmDesc_t smDesc)
Return the identifier of the current state in a state machine (or zero if the state machine is stoppe...
Definition: FwSmCore.c:222
A transition is added to a state machine with an illegal (out-of-range) state destination.
FwSmTestOutcome_t FwSmTestCaseTrans7()
Verify the order of evaluation of guards on transitions out of a proper state.
FwSmDesc_t FwSmMakeTestSM4(struct TestSmData *smData)
Operation to create and configure the state machine SM4.
Definition: FwSmMakeTest.c:296
FwSmDesc_t FwSmMakeTestSM14(struct TestSmData *smData)
Operation to create and configure a state machine where the choice pseudo-state is used both to split...
Definition: FwSmMakeTest.c:704
FwSmDesc_t FwSmMakeTestSM16_2(struct TestSmData *smData)
Operation to create and configure a state machine to verify the order of evaluation of guards...
Definition: FwSmMakeTest.c:823
FwSmTestOutcome_t FwSmTestCaseSelfTrans1()
Test a self-transition on a simple state (state S2 of SM4).
void FwSmSetData(FwSmDesc_t smDesc, void *smData)
Set the pointer to the state machine data in the state machine descriptor.
Definition: FwSmConfig.c:83
FwSmErrCode_t FwSmCheck(FwSmDesc_t smDesc)
Check the correctness and completeness of the configuration of a state machine descriptor.
Definition: FwSmConfig.c:350
FwSmTestOutcome_t FwSmTestCaseCheck6()
Verify the ability of FwSmCheck to detect and report the configuration error due an out-going transit...
void FwSmAddTransStaToFps(FwSmDesc_t smDesc, FwSmCounterU2_t transId, FwSmCounterS1_t srcId, FwSmAction_t trAction, FwSmGuard_t trGuard)
Create a transition from a proper state to the final pseudo-state and add it to a state machine...
Definition: FwSmConfig.c:209
#define TR_S1_FPS
A transition identifier.
Definition: FwSmMakeTest.h:48
FwSmTestOutcome_t FwSmTestCaseTrans4()
Test a transition command which triggers a transition in both the embedding and in the embedded state...
FwSmTestOutcome_t FwSmTestCaseDer2()
Create a derived state machine by extending state machine SM1 (see FwSmMakeTestSM1), override one of its actions and one of its guards, and then verify the correct behaviour of the derived state machine.
FwSmTestOutcome_t FwSmTestCaseCheck19()
Configure a state machine to have too few actions and check that FwSmCheck detects and reports this s...
FwSmDesc_t FwSmMakeTestSM16_3(struct TestSmData *smData)
Operation to create and configure a state machine to verify the order of evaluation of guards...
Definition: FwSmMakeTest.c:854
FwSmTestOutcome_t FwSmTestCaseDerConfig2()
Create a derived state machine statically and then check the configuration of the newly created state...
void FwSmPrintConfig(FwSmDesc_t smDesc, FILE *stream)
Print the configuration of the state machine to an output stream.
Definition: FwSmAux.c:23
FwSmTestOutcome_t FwSmTestCaseCheck16()
Verify the ability of the configuration functions of a state machine to detect and report the followi...
FwSmTestOutcome_t FwSmTestCaseCheck14()
Verify the ability of the configuration functions of a state machine to detect and report the followi...
#define TR6
A transition identifier.
Definition: FwSmMakeTest.h:66
FwSmTestOutcome_t FwSmTestCaseExecute1()
Test the Execute command in a configuration where the command only causes the do-action of a simple s...
#define TR5
A transition identifier.
Definition: FwSmMakeTest.h:64
int counter_2
Counter incremented by the transition actions.
Definition: FwSmMakeTest.h:105
FwSmCounterS1_t nOfGuards
the number of guards in the state machine
Definition: FwSmPrivate.h:315
#define STATE_S3
A state identifier.
Definition: FwSmMakeTest.h:40
FwSmTestOutcome_t FwSmTestCaseCheck3()
Verify the ability of FwSmCheck to detect and report the configuration error due to a transition in a...
FwSmDesc_t FwSmMakeTestSM9Static(struct TestSmData *smData)
Operation to create and configure the state machine SM5 (see FwSmMakeTestSM9 and figure below) static...
Definition: FwSmMakeTest.c:567
Test case failure.
Definition: FwSmTestCases.h:31
FwSmGuard_t * smGuards
the transition guards in the state machine
Definition: FwSmPrivate.h:309
void SmDummyAction(FwSmDesc_t smDesc)
Dummy action which returns without doing anything.
Definition: FwSmCore.c:40
A state is added twice to the same state machine.
FwSmTestOutcome_t FwSmTestCasePrint2()
Verify the ability of the FwSmPrintConfig function to write to a file the configuration of a state ma...
FwSmTestOutcome_t FwSmTestCaseStart1()
Test the Start command on a simple state machine where the initial pseudo-state is directly connected...
SmBaseDesc_t * smBase
pointer to the base descriptor
Definition: FwSmPrivate.h:305
FwSmTestOutcome_t FwSmTestCaseTransErr2()
Test a transition which has a choice pseudo-state as both source and destination. ...
FwSmTestOutcome_t FwSmTestCaseStop3()
Test the Stop command for a state machine with an embedded state machine.
FwSmDesc_t FwSmMakeTestSM9(struct TestSmData *smData)
Operation to create and configure a degenerate state machine with no transitions other than the initi...
Definition: FwSmMakeTest.c:548
int counter_1
Counter incremented by the state actions.
Definition: FwSmMakeTest.h:103
void FwSmAddState(FwSmDesc_t smDesc, FwSmCounterS1_t stateId, FwSmCounterS1_t nOfOutTrans, FwSmAction_t entryAction, FwSmAction_t exitAction, FwSmAction_t doAction, FwSmDesc_t esmDesc)
Create a state with the given characteristics and add it to a state machine.
Definition: FwSmConfig.c:92
FwSmTestOutcome_t FwSmTestCaseDescStatic2()
Verify the correct behaviour of a state machine descriptor which was created statically using the ser...
FwSmTestOutcome_t FwSmTestCaseDer3()
Create a derived state machine by extending state machine SM6 (see FwSmMakeTestSM6) and then verify t...
A transition is added to a state machine with a source which has an illegal identifier.
Declaration of the static creation interface for a FW State Machine.
FwSmTestOutcome_t FwSmTestCaseDescDir1()
Verify the correct behaviour of a state machine descriptor which was created by directly instantiatin...
void FwSmAddTransIpsToSta(FwSmDesc_t smDesc, FwSmCounterS1_t destId, FwSmAction_t trAction)
Create a transition from the initial pseudo-state to a proper state and add it to a state machine...
Definition: FwSmConfig.c:181
The number of guards added to the state machine is smaller than the number of guards declared when th...
FwSmTestOutcome_t FwSmTestCaseCheck8()
Verify the ability of the configuration functions of a state machine to detect and report the followi...
void FwSmAddTransCpsToSta(FwSmDesc_t smDesc, FwSmCounterS1_t srcId, FwSmCounterS1_t destId, FwSmAction_t trAction, FwSmGuard_t trGuard)
Create a transition from a choice pseudo-state to a proper state and add it to a state machine...
Definition: FwSmConfig.c:203
The overridden action in a derived state machine does not exist.
Return codes of a function which has completed execution without errors.
Definition: FwSmConstants.h:86
FwSmTestOutcome_t FwSmTestCaseCheck11()
Verify the ability of the state machine configuration functions to detect and report illegal configur...
Declaration of the auxiliary interface for a FW State Machine.
The state in a derived state machine to which an embedded state machine is added already holds an emb...
signed char FwSmCounterS1_t
Type used for signed counters with a "short" range.
Definition: FwSmConstants.h:79
FwSmTestOutcome_t FwSmTestCaseCheck18()
Configure a transitions to exceed the maximum number of actions and the maximum number of guards and ...
A state or choice pseudo-state is added to a state machine which has more out-going transitions than ...
void FwSmEmbed(FwSmDesc_t smDesc, FwSmCounterS1_t stateId, FwSmDesc_t esmDesc)
Embed a state machine in a state of a derived state machine.
Definition: FwSmConfig.c:494
FwSmTestOutcome_t FwSmTestCaseDummySM1()
Verify the behaviour of a degenerate state machine which has no states.
The number of actions in the base state machine is not the same as in the derived state machine...
FwSmDesc_t FwSmMakeTestSM13(struct TestSmData *smData)
Operation to create and configure a state machine where the &#39;execute&#39; transition has a choice pseudo-...
Definition: FwSmMakeTest.c:679
void FwSmReleaseRec(FwSmDesc_t smDesc)
Recursively release the memory which was allocated when the state machine descriptor was created...
Definition: FwSmDCreate.c:239
Declaration of the internal data structures of the FW State Machine Module.
FwSmDesc_t FwSmMakeTestSM2(struct TestSmData *smData)
Operation to create and configure the state machine SM2.
Definition: FwSmMakeTest.c:243
Test case success.
Definition: FwSmTestCases.h:27
A state is added to a state machine with an illegal (out-of-range) identifier.
int fwSm_logMarker[LOG_ARRAY_SIZE]
Log array where state machine operations write their marker.
Definition: FwSmMakeTest.c:30
FwSmCounterS1_t FwSmGetCurStateEmb(FwSmDesc_t smDesc)
Return the identifier of the current state of the state machine embedded in the current state (the su...
Definition: FwSmCore.c:227
FwSmTestOutcome_t FwSmTestCaseExecute5()
Verify the &#39;Execute&#39; command when it triggers a transition from a state to a choice pseudo-state and ...
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